A/D, D/C Converters for Image Signal Processing
MN655431SH
Low Power 8-Bit CMOS A/D Converter for Image Processing
Overview
The MN655431SH is an 8-bit CMOS analog-to-digital
converter with a maximum conversion rate of 15 MSPS.
It uses a half flash structure based on chopper com-
parators and achieves both high speed and low power con-
sumption with multiplex processing.
It provides separate power supply pins for the circuits
driving the low-voltage digital output pins.
Pin Assignment
Features
Maximum conversion rate: 15 MSPS (min.)
Linearity error:
±0.5
LSB (typ.)
Differential linearity error:
±0.4
LSB (typ.)
Power supply voltage: 4.40 to 5.25 V
Power consumption: 90 mW (typ.)
DV
DDL
DV
SS
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
DV
DD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DV
SS
V
RB
V
RBS
AV
SS
AV
SS
V
IN
AV
DD
V
RT
V
RTS
AV
DD
AV
DD
DV
DD
Applications
Digital television receivers
Digital video equipment
Digital image processing equipment
SSOP024-P-0300
(TOP VIEW)
1
MN655431SH
Block Diagram
A/D, D/C Converters for Image Signal Processing
AV
DD
14
11
DV
DD
13
AV
DD
DV
SS
AV
SS
AV
SS
23
21
22
20
19
18
17
24
16
Lower comparator
(4 bits)
15
AV
DD
Reference
resistor
Lower comparator
(4 bits)
Encoder (4 bits)
Encoder (4 bits)
Lower comparator (4 bits)
Clock generator
Data latch
Encoder (4 bits)
10
D1
D7(MSB)
DV
DDL
D0(LSB)
D3
D5
2
DV
SS
CLK
D2
D4
D6
12
2
3
4
1
5
6
7
8
9
DV
DD
V
RBS
V
RTS
V
RB
V
RT
V
IN
A/D, D/C Converters for Image Signal Processing
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
DV
DDL
DV
SS
D0
D1
D2
D3
D4
D5
D6
D7
DV
DD
CLK
DV
DD
AV
DD
AV
DD
V
RTS
V
RT
AV
DD
V
IN
AV
SS
AV
SS
V
RBS
V
RB
DV
SS
Function Description
Power supply for digital output circuits
Ground for digital circuits
Digital output (LSB)
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output (MSB)
Power supply for digital circuits
Sampling clock
Power supply for digital circuits
Power supply for analog circuits
Power supply for analog circuits
Power supply for reference voltage (TOP)
Reference voltage (TOP)
Power supply for analog circuits
Analog input
Ground for analog circuits
Ground for analog circuits
Power supply for reference voltage (BOTTOM)
Reference voltage (BOTTOM)
Ground for digital circuits
Ta=25˚C
MN655431SH
Absolute Maximum Ratings
Parameter
Power supply voltage
Power supply voltage for digital outputs
Symbol
V
DD
DV
DDL
V
I
V
O
T
opr
T
stg
Rating
– 0.3 to +7.0
– 0.3 to +V
DD
+0.3
AV
SS
– 0.3 to V
DD
+0.3
DV
SS
– 0.3 to V
DD
+0.3
–20 to +70
–55 to +125
Unit
V
V
V
V
˚C
˚C
Input voltage
Output voltage
Operating ambient temperature
Storage temperature
3
MN655431SH
A/D, D/C Converters for Image Signal Processing
V
DD
=AV
DD
=DV
DD
=5.0V, DV
DDL
=3.5V, V
SS
=AV
SS
=DV
SS
=0V, Ta=25˚C
Recommended Operating Conditions
Parameter
Power supply voltage
Power supply voltage for digital outputs
Symbol
V
DD
DV
DDL
V
IH
V
IL
V
RT
V
RB
t
WH
t
WL
V
AIN
Symbol
I
DD
RES
E
L
E
D
F
c(max.)
f
CLK
D
R
I
OH
I
OL
t
d
C
I
f
CLK
=15MHz
V
RT
=3.5V
min
4.50
3.4
2.4
V
SS
3.3
V
SS
30
30
V
SS
typ
5.00
max
5.25
3.6
V
DD
0.8
V
DD
1.5
Unit
V
V
V
V
V
V
ns
ns
Digital input
voltage
Reference voltage
"H" level
"L" level
"H" level
"L" level
"H" level pulse width
"L" level pulse width
Clock
Analog input voltage
V
DD
min
typ
18
8
±0.5
±0.4
15
1
2
15
V
RT
–V
RB
–2
2
30
18
45
±1.3
±0.7
max
26
V
Unit
mA
bit
LSB
LSB
MSPS
MHz
V
mA
mA
ns
pF
Electrical Characteristics
Parameter
Power supply voltage
Resolution
Linearity error
Differential linearity error
Maximum conversion rate
Clock frequency
Analog input dynamic range
V
DD
=AV
DD
=DV
DD
=5.0V, DV
DDL
=3.5V, AV
SS
=DV
SS
=0V, Ta=25˚C
Conditions
f
CLK
= 15 MHz
(includes reference power supply)
V
RB
=1.5V
Output
current
"H" level
"L" level
V
OH
=DV
DDL
– 0.8V
V
OL
= 0.4V
Output delay time
Analog input capacitance
4
A/D, D/C Converters for Image Signal Processing
Timing Chart
MN655431SH
The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital
output 2.5 clock cycles later at the rising edge of the clock signal.
t
WH
Clock
t
WL
Analog input
N
N+1
N–2
t
d
(30ns)
N+2
N–1
N+3
N
N+4
N+1
Data output
N–3
Note: The circles indicate analog signal sampling points.
5
测试/测量
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