A/D, D/C Converters for Image Signal Processing
MN65742
6-Bit, 2-Channel CMOS A/D Converter
Overview
The MN65742 is a 6-bit, 2-channel CMOS analog-to-
digital converter. It uses a totally parallel structure based
on differential comparators to achieve high-speed opera-
tion.
Pin Assignment
CLK
AV
DD
AV
SS
VRT
N.C.
VINA
AV
SS
AV
DD
POWD
VRM
V
INB
VRB
AV
SS
AV
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DA5
DA4
DA3
DA2
DA1
DA0
AV
SS
AV
DDL
DB5
DB4
DB3
DB2
DB1
DB0
Features
Resolution: 6 bits
Maximum conversion rate: 60 MSPS (min.)
Linearity error:
±1.3
LSB (typ.)
Differential linearity error:
±1.3
LSB (typ.)
Analog input voltage level:
1.5 V
p-p
(typ.) (1.0 to 2.5 V)
Power supply voltage: 5.0
±0.25
V
3.0 to 5.25 V (power supply for output pins)
Power consumption: 250 mW (typ.) (F
C
= 60 MSPS,
not including reference current)
Applications
Digital satellite broadcasting receivers
Digital video equipment
Multimedia equipment
Communications equipment
(TOP VIEW)
SOP028-P-0375
1
MN65742
Block Diagram
A/D, D/C Converters for Image Signal Processing
AV
DD
AV
DD
AV
DD
AV
SS
AV
SS
13 AV
SS
22 AV
SS
10 VRM
V
INA
V
INB
14
12
Channel B (Bch.)
Channel A (Ach.)
Comparator
Encoder
Encoder
Comparator
Reference
resistor array
Clock
generator
Output logic
circuits
Output logic
circuits
Clock
generator
11
Reference
resistor array
15
16
17
18
19
20
23
24
25
26
27
28
POWD 9
CLK
DA0
DA1
DA2
DA3
DA4
DA5
DB0
DB1
DB2
DB3
DB4
DB5
2
AV
DDL
21
1
5 N.C.
2
8
3
7
4
V
RB
V
RT
6
A/D, D/C Converters for Image Signal Processing
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
CLK
AV
DD
AV
SS
V
RT
N.C.
V
INA
AV
SS
AV
DD
POWD
VRM
V
INB
V
RB
AV
SS
AV
DD
DB0
DB1
DB2
DB3
DB4
DB5
AV
DDL
AV
SS
DA0
DA1
DA2
DA3
DA4
DA5
Function Descriptions
Clock input
Power supply for analog circuits
Ground for analog circuits
Reference voltage (top)
No connection
Analog signal input pin
Ground for analog circuits
Power supply for analog circuits
Power-down selection pin
Intermediate reference voltage
Analog signal input pin
Reference voltage (bottom)
Ground for analog circuits
Power supply for analog circuits
Digital output pin
Digital output pin
Digital output pin
Digital output pin
Digital output pin
Digital output pin
Power supply pin for digital output circuits
Ground for analog circuits
Digital output pin
Digital output pin
Digital output pin
Digital output pin
Digital output pin
Digital output pin
Ta=25˚C
MN65742
Absolute Maximum Ratings
Parameter
Power supply voltage
Symbol
AV
DD
AV
DDL
V
I
V
O
T
opr
T
stg
Rating
– 0.3 to +7.0
– 0.3 to AV
DD
+0.3
– 0.3 to AV
DD
+0.3
– 0.3 to AV
DD
+0.3
–20 to +70
–55 to +125
Unit
V
V
V
V
˚C
˚C
Power supply voltage for output circuits
Input voltage
Output voltage
Operating ambient temperature
Storage temperature
3
MN65742
A/D, D/C Converters for Image Signal Processing
AV
DD
=5.0V, AV
DDL
=3.3V, AV
SS
=0V, Ta=25˚C
Recommended Operating Conditions
Parameter
Power supply voltage
Power supply voltage for digital outputs
Digital input
voltage
Reference
voltage
Clock
"H" level
"L" level
"H" level
"L" level
"H" level pulse width
"L" level pulse width
Analog input voltage
Symbol
V
DD
DV
DDL
V
IH
V
IL
V
RT
V
RB
t
WH
t
WL
V
AIN
min
4.75
3.00
2.2
AV
SS
2.0
0.5
7
7
AV
SS
typ
5.00
3.30
max
5.25
5.25
AV
DD
0.8
Unit
V
V
V
V
V
V
ns
ns
2.5
1.0
3.5
2.0
AV
DD
V
Electrical Characteristics
Parameter
Current
AV
DD
consumption
AV
DDL
Resolution
Linearity error
Differential linearity error
Maximum conversion rate
Clock frequency
Analog input dynamic range
Output
current
"H" level
"L" level
AV
DD
=5.0V, AV
DDL
=3.3V, AV
SS
=0V, V
RT
=2.5V, V
RB
=1.0V, Ta=25˚C
Symbol
Conditions
I
DD
f
CLK
= 60 MSPS
(not including reference current)
I
DDL
RES
E
L
E
D
F
C(max.)
f
CLK
D
R
I
OH
I
OL
t
d
C
I
V
OH
=DV
DDL
– 0.8V
V
OL
=0.4V
C
L
=20pF
f
CLK
=60MSPS
min
typ
47
3
6
±0.7
±0.7
max
80
6
±1.3
±1.3
60
V
RT
–V
RB
–2.0
Unit
mA
mA
bit
LSB
LSB
MSPS
MHz
V
mA
mA
ns
pF
60
1
1.4
2.0
3
7
20
11
Output delay time
Analog input capacitance
4
A/D, D/C Converters for Image Signal Processing
Timing Chart
MN65742
The chip samples the analog input at the rising edge of the clock signal and provides the corresponding digital
output one clock cycle later at the rising edge of the clock signal.
t
WH
t
WL
Analog input
N
t
sd
N+1
N+2
N+3
Clock
1.5V
Data output
N-2
N-1
N
N+1
N+2
N+3
1.5V
t
d
Note: The circles indicate analog signal sampling points.
5
stm32/stm8
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