LSIs for DAB
MN66710
Full-Function DAB Receiver LSI
I
Overview
The MN66710 is a single-chip digital signal processing LSI for a DAB (digital audio broadcast) receiver, including
OFDM demodulation, service selection, error correction, and MPEG audio decoding. The MN66710 conforms to the
European DAB standard (ETS 300 401). Since the MN66710 includes an on-chip A/D converter for the IF signal input,
it can be directly input the 3.072 MHz center frequency analog IF signal output from the DAB high-frequency circuit.
A DAB receiver is implemented easily by combining MN66710 with a small number of additional components, in
particular, 4M DRAMs for working memory, audio D/A converters, microcontrollers, and etc.
I
Features
•
The DAB signal-processing block is integrated on a single chip. (with external 4M DRAMs)
•
Supports all of DAB modes I, II, III, and IV.
•
Achieves a processing data rate of up to 1.536 Mbps.
•
Up to 4 MSC sub-channels can be selected.
•
MPEG audio decoder (Also supports LSF.)
•
Supports the standard audio D/A converter interface.
•
Digital audio output unit conforming EIAJ CP-1201 (External driver required.)
•
RDI output and dedicated audio RDI input units (For high capacity mode only.)
•
F-PAD and X-PAD extraction function
•
AIC support function provided in hardware.
•
Supports multiplex restructuring with no interruption of the audio signal.
•
TII decoding function (basic mode)
•
Low supply voltage: 3.3 V±0.3 V
•
Low power: Under 500 mW
I
Applications
•
DAB (digital audio broadcast) receivers
Publication date: November 2001
SDC00041BEM
1
MN66710
I
Block Diagram
RAD0 to RAD9
ADVRT
ADIN
ADVRB
ADC
I/Q
Gen.
OFDM
De-Interleave
RDT0 to RDT3
NRAMOE
NRRAS
NRCAS
NRAMWE
IQMOD
NULDET
FSYO
MCLK24
NRST
CTLDAT
CTLCLK
CTLLR
CIRSYN
DSPMON0 to
DSPMON6
DSPMNEN
MPUSYNC
MPUMOD
MPUTX
MPURX
MPUCLK
NPADRDY
TEST0 to TEST3
DAI I/F
MPU I/F
Audio
I/F
DAC I/F
AFC
CIR
I/F
Timing
Gen.
DSP Core
(Sync/AFC/MPEG Dec.)
Viterbi Dec.
UEP/EEP
FDAT3
FERF3
FCLK3
FWFIC
FW1 to FW4
FD3EN
RDIOUT
RDI I/F
RDIIN
RDIU0 to RDIU5
SDAT
SCLK
SLRCK
SMCK
AUXDAT
DAOUT
2
SDC00041BEM
MN66710
I
Pin Arrangement
DSPMON2
DSPMON3
DSPMON4
DSPMON5
DSPMON6
DSPMNEN
CIRSYN
CTLLR
CTLCLK
CTLDAT
VSS4
VDD3
FSYO
NULDET
AVSS
ADVRB
ADIN
ADVRT
AVDD
VREF
IQMOD
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
DSPMON1
DSPMON0
VSS3
RDT3
RDT2
RDT0
RDT1
NRAMWE
NRRAS
RAD9
NRCAS
NRAMOE
RAD8
RAD7
VDD2
VSS2
RAD0
RAD1
RAD2
RAD3
RAD6
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
RAD5
RAD4
FDAT3
FERF3
FCLK3
FWFIC
FW1
FW2
FW3
FW4
FD3EN
VDD1
VSS1
RDIOUT
RDIU5
RDIU4
RDIU3
RDIIN
RDIU2
RDIU1
RDIU0
Note) Do not leave any of the VDD and VSS pins open.
Connect the TEST0 to TEST3 pin to VSS.
MPUSYNC
NPADRDY
MPUCLK
MPURX
MPUTX
MPUMOD
TEST0
TEST1
TEST2
TEST3
NRST
VSS0
VDD0
MCLK24
MCLKO
DAOUT
AUXDAT
SMCK
SLRCK
SCLK
SDAT
(TOP VIEW)
SDC00041BEM
3
MN66710
I
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Pin Name
MPUSYNC
NPADRDY
MPUCLK
MPURX
MPUTX
MPUMOD
TEST0
TEST1
TEST2
TEST3
NRST
VSS0
VDD0
MCLK24
MCLKO
DAOUT
AUXDAT
SMCK
SLRCK
SCLK
SDAT
RDIU0
RDIU1
RDIU2
RDIIN
RDIU3
RDIU4
RDIU5
RDIOUT
VSS1
VDD1
FD3EN
FW4
FW3
FW2
I/O
O
O
I
I
O
I
I
I
I
I
I
I
O
O
I
O
O
O
O
O
O
O
I
O
O
I
O
I
O
O
O
Descriptions
Microcontroller operation reference signal
PAD data ready signal
Microcontroller interface data clock
Microcontroller interface reception data
Microcontroller interface transmission data
Microcontroller interface mode
Test mode setup
Test mode setup
Test mode setup
Test mode setup
Master reset input
Digital system ground
Digital system power supply
Master clock input (24.576 MHz)
Master clock oscillator circuit output
SPDIF digital audio interface output
Audio A/D converter serial data input
Auxiliary input A/D converter connection
For use with a crystal oscillator element
Normally connect to V
SS
Normally connect to V
SS
Normally connect to V
SS
Normally connect to V
SS
The IC is reset when this input is set low
Note
Timing signal with a 24 ms period
Indicates that the PAD register can be read
Audio A/D and D/A converter master clock Outputs a 256 fs clock
Audio A/D and D/A converter left/right clock
Audio A/D and D/A converter serial clock output
Audio D/A converter serial data output Audio output D/A converter connection
Auxiliary outputs for RDI expansion
Auxiliary outputs for RDI expansion
Auxiliary outputs for RDI expansion
RDI input
Auxiliary outputs for RDI expansion
Auxiliary outputs for RDI expansion
Auxiliary inputs for RDI expansion
RDI output
Digital system ground
Digital system power supply
General-purpose data output enable
General-purpose output window 4
General-purpose output window 3
General-purpose output window 2
Output enable for FDAT3, FERF3, and FCLK3
Window for sub-channel 4
Window for sub-channel 3
Window for sub-channel 2
Normally left open
Normally left open
Normally left open
RDI back channel (audio only)
Normally left open
Normally left open
Normally connect to V
SS
For high capacity mode only
4
SDC00041BEM
MN66710
I
Pin Descriptions (continued)
Pin No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin Name
FW1
FWFIC
FCLK3
FERF3
FDAT3
RAD4
RAD5
RAD6
RAD3
RAD2
RAD1
RAD0
VSS2
VDD2
RAD7
RAD8
NRAMOE
NRCAS
RAD9
NRRAS
NRAMWE
RDT1
RDT0
RDT2
RDT3
VSS3
DSPMON0
DSPMON1
DSPMON2
DSPMON3
DSPMON4
DSPMON5
DSPMON6
DSPMNEN
CIRSYN
CTLLR
CTLCLK
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
O
O
O
Descriptions
General-purpose output window 1
General-purpose output window 0
General-purpose data output clock
Note
Window for sub-channel 1 (audio)
FIC window
1.536 MHz continuous clock
General-purpose data output error flag Flag that indicates Viterbi-corrected bits
General-purpose data output data
External DRAM address, bit 4
External DRAM address, bit 5
External DRAM address, bit 6
External DRAM address, bit 3
External DRAM address, bit 2
External DRAM address, bit 1
External DRAM address, bit 0
Digital system ground
Digital system power supply
External DRAM address, bit 7
External DRAM address, bit 8
External DRAM output enable
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
External DRAM column address strobe For connecting external DRAM
External DRAM address, bit 9
External DRAM row address strobe
External DRAM write enable
External DRAM data, bit 1
External DRAM data, bit 0
External DRAM data, bit 2
External DRAM data, bit 3
Digital system ground
DSP monitor, bit 0
DSP monitor, bit 1
DSP monitor, bit 2
DSP monitor, bit 3
DSP monitor, bit 4
DSP monitor, bit 5
DSP monitor, bit 6
DSP monitor output enable
CIR display cycle signal
Normally left open
Normally left open
Normally left open
Normally left open
Normally left open
Normally left open
Normally left open
A low level disables DSP monitor output
CIR monitor display trigger signal
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
For connecting external DRAM
AFC/CIR D/A converter left/right clock For AFC control and CIR monitor display
AFC/CIR D/A converter clock
SDC00041BEM
For AFC control and CIR monitor display
5
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