For Video Equipment
MN88831
PCM Audio Decoder LSI for Satellite Broadcasting Tuners
(Includes Built-In Digital Filter and D/A Converter)
Overview
The MN88831 greatly streamlines set design by incor-
porating a satellite broadcasting PCM audio decoder, a
switched capacitor D/A converter, and analog post filter
to a single chip.
Pin Assignment
PO0/MTO
PI2
PI1
DV
DD
BSTIN
BSTRM
SYNCF
DCDI
ECDO
P2M
NAMODE
BPO
36
35
34
33
32
31
30
29
28
27
26
25
Features
Built-in digital filter using 8-fold oversampling
Built-in tertiary
∆-∑
noise shaping D/A converter
Reduced jitter noise through use of switched
capacitor configuration
Built-in analog post filter
Built-in digital de-emphasis circuit
Choice of microcomputer interfaces with selector pin:
3-wired serial interface or I
2
C interface
Muting function supporting following settings
• Pay-per-view flag detection
• Error frequency detection
• Detection of control code bit-7
Built-in general-purpose microcomputer I/O port
Bit stream input pin supporting 0.4 V
P-P
input
PO1
PO2
PO3
PO4
PC
DV
SS
IV
I
IV
O
XI
XO
IIN
OIN
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
NTI
NLOCK
NRES
DV
SS
AV
DDR
V
REF
OUTR
AV
SSR
BIAS
AV
SSL
OUTL
AV
DDL
Applications
Satellite broadcasting tuners (BS, CS)
DV
DD
PO5
PO6/LIBP
IFSEL
TES0
TES1
CHV
CWO/IFMOD
CS/SA
CCK/SCL
CTLI/SDA
DV
SS
(TOP VIEW)
QFP048-P-1212A
V
REF
BIAS
BPO
MTI
IV
O
MN88831
Block Diagram
IV
I
25
24
44
19
16
Data output control
Digital audio interface
43
ECDI
Digital filter
Digital de-emphasis
29
Range bit detection and
correction.
Pay-per-view flag detection
SW2
ECDO
∆–Σ
noise shaper
28
Duplex error
detection and
correction
(DE)
A mode data expansion
Incompatible data range detection
Data interpolation
Muting
SYNCF
(LIBP)
(MTO)
De-interleaving
Switched capacitor D/A
converter
30
NLOCK
23
Frame synchronization
detection
Timing generator
BSTRM
31
1T
Analog post filter
Descramble control code
integration and detection
SW1
BSTIN
Microcomputer interface:
Serial or I
2
C bus
34,35
32
NRES
22
Clock generator
VCO
Differential decoder
serialization
8
41
36
7
4
9
3
27
26
10
11
Timing generator
for
D/A converter block
(D/A converter block)
14
18
46
P2M
CHV
IFSEL
CS/SA
PI1,PI2
CCK/SCL
PO6/LIBP
PO0/MTO
NAMODE
CTLI/SDA
PO1 to PO5
CWO/IFMOD
For Video Equipment
45
47
48
PC
XO
OUTL
OUTR
XI
IIN
QIN
For Video Equipment
Absolute Maximum Ratings
Parameter
Power supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
V
I
V
O
I
O
P
D
T
opr
T
stg
Ratings
– 0.3 to 7.0
– 0.3 to V
DD
+0.3
– 0.3 to V
DD
+0.3
25
480
–20 to +70
–55 to +125
MN88831
Unit
V
V
V
mA
mW
˚C
˚C
Notes:
1. The above ratings represent the maximum values that may be applied without damaging the chip, not the limits for guaranteed
operation.
2. If the chip is to be used in the presence of strong electric fields—under a CRT tube, for example—apply shielding to the package
surface to ensure proper operation.
3. The power dissipation is for an ambient temperature (Ta) of 70˚C.
4. The voltages applied to the pins CCK/SCL, CTLI/SDA, CWO/IFMOD, PO0/MTO, PO1–PO5, and PO6/LIBP must be within
the range between –0.3V and 5.5V when the power is off.
Operating Conditions
Parameter
Power supply voltage for
digital circuits
Power supply voltage for
analog circuits
XI clock frequency
XI clock frequency
XI clock input amplitude
BSTIN input amplitude
Ambient temperature during
operation
Notes:
1. *1 & *2:
DV
SS
=AV
SS
=0V
Symbol
DV
DD
AV
DD
f
XI
f
XI
—
—
Ta
Test Conditions
(*1)
(*2)
CHV="H" (256fs mode)
CHV="L" (384fs mode)
C cut input
C cut input
min
4.5
4.5
typ
5.0
5.0
12.288
18.432
max
5.5
5.5
Unit
V
V
MHz
MHz
0.8
0.35
–20
0.5
3.0
+70
V
P-P
V
P-P
˚C
For the logic portions of the microcomputer interface, DV
DD
min = 4.0V.
AV
DD
covers both AV
DDL
and AV
DDR
.
AV
SS
covers both AV
SSL
and AV
SSR
.
Analog characteristics are only guaranteed for DV
DD
= AV
DD
= 5.0V.
2. Always use low-impedance external connections for V
DD
and V
SS
.
Always connect the two through a bypass capacitor of at least 0.01 µF to ensure proper operation.
3. Keep the NRES pin (pin No. 22) at "L" level to prevent operation error of the CTLI/SDA pin in the I
2
C interface at voltages
lower than the guaranteed operating power supply voltage.
MN88831
Electrical Characteristics
(1) DC characteristics
AV
DD
=DV
DD
=4.5 to 5.5V, AV
SS
=DV
SS
=0V, Ta= –20 to +70˚C
For Video Equipment
Parameter
Symbol
I
DD1
Test Conditions
No load, V
DD
=5.5V
384fs
No load, V
DD
=5.5V
256fs
min
typ
56
56
max
80
80
Unit
mA
mA
Power supply current
I
DD2
Digital input pins 1
(*1)
"H" level input voltage
"L" level input voltage
Digital input pins 2
(*2)
"H" level input voltage
"L" level input voltage
Digital output pins 1
(*3)
"H" level output voltage
"L" level output voltage
Digital output pins 2
(*4)
"L" level output voltage
High-impedance output
leakage current
Digital output pins 3
(*5)
"L" level output voltage
High-impedance output
leakage current
Analog output pins
VREF pin output pin
BIAS pin output pin
IVI-IVO inverter
Inverter input threshold
voltage
Notes:
V
IH1
V
IL1
V
IH2
V
IL2
V
OH1
V
OL1
V
OL2
I
LO
I
OH1
= –1mA
I
OL1
=+1mA
I
OL2
=+1mA
V
O
=High-impedance state
V
I
=0V to DV
DD
I
OL3
=+1mA
V
I
=0V to DV
DD
V
NRES
=0V to 0.5V
0.7
×
DV
DD
DV
SS
0.8
×
DV
DD
DV
SS
DV
DD
– 0.8
DV
DD
0.3
×
DV
DD
DV
DD
0.2
×
DV
DD
V
V
V
V
V
0.5
0.5
±10
V
V
µA
V
OL3
I
LO2
0.5
±50
V
µA
V
REF
V
BIAS
0.45
×
AV
DD
0.5
×
AV
DD
V
V
V
TI
0.5
×
DV
DD
± 0.75
V
*1: IFSEL, TES0, TES1, CHV, MTI, ECDI, PI1, PI2, IIN, QIN, CWO/IFMOD (C3, C4 only), IVI (C5 only)
*2: CS/SA, CCK/SCL, NRES, CTLI/SDA (C6, C7 only)
*3: NLOCK, BPO, NAMODE, P2M, ECDO, SYNCF, BSTRM, PC
*4: PO0/MTO, PO1 to PO6, CWO/IFMOD, PC (C12 only)
*5: CTLI/SDA
For Video Equipment
Application Circuit Example
MN88831
MN88831’s built-in
final differential addition filter
Switched capacitor block output
OUTL–
OUTL+
MI
BIAS
OUT
approx.
100Ω
OUTL
680Ω 33µF
18kΩ
PI
4700pF
BIAS
+
22µF
Reference voltage
Bias voltage for operational amplifier
V
REF
+
22µF
Structure of Analog Post Filter and Sample Analog Connections
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