High Reliability Series Serial EEPROM Series
I C BUS
Serial EEPROMs
BR24A01A-WM, BR24A02-WM, BR24A04-WM, BR24A08-WM,
BR24A16-WM, BR24A32-WM, BR24A64-WM
●Description
2
BR24A□□-WM series is a serial EEPROM of I C BUS interface method.
●Features
2
・
Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock(SCL) and serial
data(SDA)
・
Other devices than EEPROM can be connected to the same port, saving microcontroller port
・
2.5V~5.5V single power source action most suitable for battery use
・
Page write mode useful for initial value write at factory shipment
・
Highly reliable connection by Au pad and Au wire
・
Auto erase and auto end function at data rewrite
・
Low current consumption
*1
At write operation (5V)
: 1.2mA (Typ.)
At read operation (5V)
: 0.2mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
・
Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
*2
・
SOP8/SOP-J8 compact package
・
Data rewrite up to 1,000,000 times
・
Data kept for 40 years
Page write
・
Noise filter built in SCL / SDA terminal
Number
of
8Byte
16Byte
32Byte
・
Shipment data all address FFh
Pages
*1
*2
BR24A32-WM、BR24A64-WM : 1.5mA
Refer to following list
Product
number
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
2
●BR24A
series
Capacity
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
32Kbit
64Kbit
Bit format
128×8
256×8
512×8
1K×8
2K×8
4K×8
8K×8
Type
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
Power source
Voltage
2.5½5.5V
2.5½5.5V
2.5½5.5V
2.5½5.5V
2.5½5.5V
2.5½5.5V
2.5½5.5V
SOP8
●
●
●
●
●
●
●
SOP-J8
●
●
●
●
●
●
●
Jan. 2009
●Absolute
maximum ratings (Ta=25℃)
Parameter
Impressed voltage
Permissible
dissipation
Storage
temperature range
Action
temperature range
Terminal voltage
4.5mW
(
symbol
V
CC
Pd
Tstg
Topr
－
*1,*2
)
●Memory
cell characteristics (Ta=25℃, Vcc=2.5½5.5V)
Unit
V
mW
℃
℃
V
Parameter
Number of data rewrite times
*1
Data hold years
○Shipment
data all address FFh
*1
Limits
－0.3½+6.5
450 (SOP8)
*1
450 (SOP-J8)
*2
－65½+125
－40½+105
－0.3½Vcc+1.0
Limits
Min.
1,000,000
40
*1
Typ.
－
－
Max.
－
－
Unit
Times
Years
Not 100% TESTED
When using at Ta=25℃ or higher,
to be reduced per 1℃
●Recommended
operating conditions
Parameter
Power source voltage
Input voltage
Symbol
Vcc
V
IN
Limits
2.5½5.5
0½Vcc
Unit
V
●Electrical
characteristics (Unless otherwise specified, Ta=－40½+105℃, V
CC
=2.5½5.5V)
Parameter
“HIGH” input voltage
“LOW” input voltage
“LOW” output voltage 1
Input leak current
Output leak current
Current consumption at
action
Symbol
V
IH
V
IL
V
OL
I
LI
I
LO
I
CC1
I
CC2
I
SB
Min.
0.7Vcc
－
－
－1
－1
－
－
－
Limits
Typ.
－
－
－
－
－
－
－
－
Max.
－
0.3 Vcc
0.4
1
1
2.0
*1
3.0
*2
Unit
V
V
V
μA
μA
mA
mA
μA
Conditions
I
OL
=3.0mA (SDA)
V
IN
=0V½Vcc
V
OUT
=0V½Vcc, (SDA)
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
Vcc=5.5V,f
SCL
=400kHz
Random read, current read, sequential read
Vcc=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
*1
0.5
2.0
Standby current
◎
Radiation resistance design is not made.
BR24A01A/02/04/08/16-WM,
*2
BR24A32/64-WM
●Action
timing characteristics
Parameter
(Unless otherwise specified, Ta=
－
40½+105℃, V
CC
=2.5½5.5V)
Symbol
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
Min.
－
0.6
1.2
－
－
0.6
0.6
0
100
0.1
0.1
0.6
1.2
－
－
0
0.1
1.0
FAST-MODE
2.5V≦Vcc≦5.5V
Typ.
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
STANDARD-MODE
2.5V≦Vcc≦5.5V
Min.
Typ.
Max.
－
－
100
4.0
－
－
4.7
－
－
－
－
1.0
－
－
0.3
4.0
－
－
4.7
－
－
0
－
－
250
－
－
0.2
－
3.5
0.2
－
－
4.7
－
－
4.7
－
－
－
－
5
－
－
0.1
0
－
－
0.1
－
－
1.0
－
－
Unit
SCL frequency
Data clock “HIGH“ time
Data clock “LOW“ time
SDA, SCL rise time
*1
SDA, SCL fall time
*1
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA, SCL terminal)
WP hold time
WP setup time
WP valid time
Max.
400
－
－
0.3
0.3
－
－
－
－
0.9
－
－
－
5
0.1
－
－
－
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
*1
Not 100% tested
●FAST-MODE
and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds.
100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the maximum
action frequency, so 100kHz clock may be used in FAST-MODE. At Vcc=2.5V½5.5V , 400kHz, namely, action is made in
FASTMODE. (Action is made also in STANDARD-MODE.)
2/16
●Sync
data input / output timing
tR
SCL
tHD:STA
SDA
(入力)
(input)
tBUF
(出力)
(output)
SDA
tPD
tDH
tSU:DAT
tLOW
tHD:DAT
tF
tHIGH
SCL
DATA(1)
SDA
D1
D0
ACK
DATA(n)
ACK
½WR
WP
Stop condition
ストップコンディション
○Input
read at the rise edge of SCL
○Data
output in sync with the fall of SCL
tSU：WP
½HD：WP
Fig.1-(a) Sync data input / output timing
SCL
tSU:STA
SDA
Fig.1-(d) WP timing at write execution
SCL
tHD:STA
tSU:STO
DATA(1)
SDA
D1
D0
ACK
DATA(n)
ACK
tHIGH:WP
tWR
START BIT
STOP BIT
WP
Fig.1-(b) Start-stop bit timing
○At
write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By
setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
½WR
Stop condition
Start condition
SCL
SDA
D0
Write data
ACK
(n-th
address)
Fig.1-(c) Write cycle timing
Fig.1-(e) WP timing at write cancel
●Block
diagram
*2
A0
1
*1
1Kbit~64Kbit EEPROM array
7bit 11bit
8bit 12bit
9bit 13b
it
10bi
t
8
8bit
Vcc
*2
A1
2
Address
decoder
*1
7bit 11bit
8bit 12bit
9bit 13b
it
10bi
t
Slave - word
address register
Data
register
7
WP
*2
A2
3
START
STOP
Control circuit
ACK
6
SCL
GND
4
＊
1
High voltage
generating circuit
7bit : BR24A01A-WM
8bit : BR24A02-WM
9bit : BR24A04-WM
Power source
voltage detection
10bit : BR24A08-WM
11bit : BR24A16-WM
12bit : BR24A32-WM
13bit : BR24A64-WM
＊
5
: BR24A04-WM
: BR24A08-WM
: BR24A16-WM
SDA
2
A0=N.C.
A0, A1=N.C.
A0, A1= N.C. A2=Don’t Use
Fig.2
Block diagram
●Pin
assignment and description
A0
A1
A2
GND
1
2
3
4
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
8
7
6
5
Vcc
WP
SCL
SDA
Terminal
name
A0
A1
A2
GND
SDA
SCL
WP
Vcc
Input /
output
Input
Input
Input
-
Input /
output
Input
Input
-
Function
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
Slave address setting
Slave address setting
Slave address setting
Reference voltage of all input / output, 0V
Not connected
Not connected
Not used
Slave address setting
Slave address setting
Slave address setting
Slave and word address, Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
3/16
●Characteristic
data (The following values are Typ. ones.)
6
5
4
VIH1,2[V]
3
2
1
0
0
3
4
5
6
Vcc[V]
Fig.3 H input voltage VIH1,2 (SCL,SDA,WP)
1.2
SPEC
SPEC
SPEC
6
5
4
VIL1,2[V]
3
2
1
0
1
2
0
3
4
5
6
Vcc[V]
Fig.4 L input voltageVIL1,2 (SCL,SDA,WP)
1
2
SPEC
Ta=105℃
Ta=-40℃
Ta=25℃
1
0.8
VOL1[V]
0.6
SPEC
Ta=105℃
Ta=25℃
0.4
0.2
Ta=105℃
Ta=-40℃
Ta=25℃
Ta=-40℃
0
0
3
4
5
6
IOL1[mA]
Fig.5 L output voltage VOL1-IOL1 (VCC=2.5V)
1
2
1.2
1
0.8
ILI[μA]
ILO[μA]
0.6
0.4
0.2
0
0
3
4
5
Vcc[V]
Fig.6 Input leak current ILI (SCL,WP)
1
2
6
Ta=105℃
Ta=25℃
Ta=-40℃
2.5
[BR24A01/02/04/08/16 series]
1
0.8
0.6
0.4
0.2
0
0
1
2
3
Vcc[V]
4
5
6
Ta=105℃
Ta=25℃
Ta=-40℃
2
ICC1[mA]
1.5
1
0.5
0
0
fSCL=400kHz
DATA=AAh
SPEC
Ta=25℃
Ta=105℃
Ta=-40℃
Fig.7 Output leak current ILO(SDA)
3
4
5
6
Vcc[V]
Fig.8 Current consumption at WRITE action ICC1
(fscl=400kHz)
[BR24A01/02/04/08/16 series]
1
2
3.5
[BR24A32/64 series]
0.6
SPEC
fSCL=400kHz
DATA=AAh
SPEC
2.5
fSCL=400kHz
DATA=AAh
3
2.5
ICC1[mA]
2
1.5
1
0.5
0
0
0.5
ICC2[mA]
0.4
0.3
0.2
0.1
0
2
ICC1[mA]
1.5
1
0.5
0
fSCL=100kHz
DATA=AAh
SPEC
Ta=105℃
Ta=25℃
Ta=25℃
Ta=105℃
Ta=-40℃
Ta=-40℃
Ta=25℃
Ta=105℃
Ta=-40℃
1
2
3
Vcc[V]
4
5
6
0
1
2
3
Vcc[V]
4
5
6
0
1
2
3
Vcc[V]
4
5
6
Fig.9 Current consumption at WRITE action ICC1
(fSCL=400kHz)
3.5
[BR24A32/64 series]
Fig.10 Current consumption at READ action ICC2
(fSCL=400kHz)
0.6
SPEC
Fig.11 Current consumption at WRITE action ICC1
(fSCL=100kHz)
2.5
SPEC
3
2.5
ICC1[mA]
2
1.5
1
0.5
0
0
1
2
3
Vcc[V]
4
5
6
Ta=25℃
Ta=105℃
Ta=-40℃
fSCL=100kHz
DATA=AAh
SPEC
0.5
ICC2[mA]
0.4
0.3
0.2
0.1
0
0
3
4
5
6
Vcc[V]
Fig.13 Current consumption at READ action ICC2
(fSCL=100kHz)
1
2
Ta=105℃
Ta=25℃
fSCL=100kHz
DATA=AAh
2
ISB[μA]
1.5
1
0.5
Ta=-40℃
Ta=105℃
Ta=-40℃
Ta=25℃
0
0
1
2
3
Vcc[V]
4
5
6
Fig.12 Current consumption at WRITE action ICC1
(fSCL=100kHz)
10000
5
Fig.14 Standby current ISB
5
SPEC2
SPEC2
1000
fSCL[kHz]
4
tHIGH [μs]
tLOW[μs]
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC1
4
3
2
1
0
0
1
2
3
Vcc[V]
4
5
6
0
3
4
5
Vcc[V]
Fig.17 Data clock "L" time tLOW
1
2
6
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC1
3
2
1
0
Ta=-40℃
Ta=25℃
Ta=105℃
SPEC1
100
SPEC2
10
1
0
1
2
3
Vcc[V]
4
5
6
Fig.15 SCL frequency fSCL
5
SPEC2
Fig.16 Data clock "H" time tHIGH
6
5
tSU:STA[μs]
4
3
2
1
0
Ta=-40℃
Ta=25℃
Ta=105℃
SPEC2
50
SPEC1,2
tHD:DAT(HIGH)[ns]
4
tHD:STA[μs]
3
2
1
0
0
1
2
3
Vcc[V]
4
5
6
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC1
0
-50
Ta=-40℃
Ta=25℃
Ta=105℃
-100
-150
-200
SPEC1
0
1
2
3
Vcc[V]
4
5
6
0
1
2
3
Vcc[V]
4
5
6
Fig.18 Start condition hold time tHD:STA
Fig.19 Start condition setup time tSU:STA
Fig.20 Input data hold time tHD:DAT(HIGH)
4/16
●Characteristic
data (The following values are Typ. ones.)
50
SPEC1,2
300
200
tSU:DAT(HIGH)[ns]
100
0
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC2
300
200
tSU:DAT(LOW)[ns]
100
0
Ta=25℃
Ta=105℃
SPEC2
SPEC1
0
tHD:DAT(LOW)[ns]
-50
Ta=105℃
Ta=25℃
SPEC1
-100
-150
-200
0
3
4
5
6
Vcc[V]
Fig.21 Input data hold time tHD:DAT(LOW)
1
2
Ta=-40℃
-100
-200
0
1
2
3
Vcc[V]
4
-100
-200
Ta=-40℃
5
6
0
1
2
Vcc[V]
3
4
5
6
Fig.22 Input data setup time tSU:DAT(HIGH)
4
5
Fig.23 Input data setup time tSU:DAT(LOW)
4
SPEC2
SPEC2
3
tPD0[μs]
3
tPD1[μs]
SPEC2
4
tBUF[μs]
3
2
1
0
0
1
2
3
Vcc[V]
4
5
6
Ta=-40℃
Ta=25℃
Ta=105℃
SPEC1
2
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC2
SPEC1
SPEC1
2
Ta=-40℃
Ta=25℃
Ta=105℃
SPEC1
1
1
SPEC2
SPEC1
0
0
1
2
3
Vcc[V]
4
5
6
0
0
1
2
3
Vcc[V]
4
5
6
Fig.24 Output data delay time tPD0
6
SPEC1,2
Fig.25 Output data delay time tPD1
0.6
0.5
Fig.26 Bus release time before transfer start tBUF
0.6
0.5
tI(SCL L)[μs]
5
Ta=25℃
tI(SCL H)[μs]
4
tWR[ms]
3
2
1
0
0
1
2
Ta=-40℃
0.4
0.3
0.2
SPEC1,2
Ta=25℃
Ta=-40℃
0.4
0.3
Ta=-40℃
Ta=105℃
Ta=105℃
0.2
0.1
0
Ta=25℃
Ta=105℃
SPEC1
0.1
0
3
Vcc[V]
4
5
6
0
1
2
3
Vcc[V]
4
5
6
0
1
2
3
Vcc[V]
4
5
6
Fig.27 Internal write cycle time tWR
0.6
0.5
tI(SDA H)[μs]
tI(SDA L)[μs]
0.4
0.3
0.2
SPEC1,2
Ta=25℃
Ta=105℃
Ta=-40℃
Fig.28 Noise removal valid time tI(SCL H)
0.6
0.5
0
Ta=-40℃
Fig.29 Noise removal valid time tI(SCL L)
0.2
SPEC1,2
0.3
Ta=25℃
tSU:WP[μs]
0.4
-0.2
Ta=105℃
Ta=25℃
Ta=-40℃
0.2
SPEC1
Ta=105℃
0.1
0
0
1
2
3
Vcc[V]
4
5
6
-0.4
0.1
0
0
3
4
5
6
Vcc[V]
Fig.31 Noise removal valid time tI(SDA L)
1
2
-0.6
0
1
2
3
Vcc[V]
4
5
6
Fig.30 Noise removal valid time tI(SDA H)
1.2
1
SPEC1,2
Fig.32 WP setup time tSU:WP
tHIGH:WP[μs]
0.8
0.6
0.4
0.2
0
0
1
2
3
Vcc[V]
4
5
6
Ta=-40℃
Ta=25℃
Ta=105℃
Fig.33 WP valid time tHIGH:WP
5/16
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