Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s)..................................+300°C
Soldering Temperature (reflow).......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
µMAX
Junction-to-Ambient Thermal Resistance (θ
JA
)..........113°C/W
Junction-to-Case Thermal Resistance (θ
JC
)................36°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
PARAMETER
ANALOG INPUT (Note 3)
Input Voltage Range
Absolute Input Voltage Range
Input Leakage Current
Input Capacitance
Input-Clamp Protection Current
STATIC PERFORMANCE (Note 4)
Resolution
No Missing Codes
Offset Error
Offset Temperature Coefficient
Gain Error
Gain Error Temperature Coefficient
Integral Nonlinearity
Differential Nonlinearity
Positive Full-Scale Error
Negative Full-Scale Error
Analog Input CMR
Power-Supply Rejection (Note 5)
Transition Noise
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25°C.) (Note 2)
SYMBOL
CONDITIONS
MIN
-V
REF
xk
-5.1
-0.1
-10
-20
16
16
-13
-12
INL
DNL
Guaranteed by design
-2.0
-0.5
-16
-16
CMR
PSR
Referred to the input
PSR vs. V
DD
, referred to the input
-72
-72
0.5
±0.5
±1
±1.5
±0.25
±0.5
±0.2
+2.0
+0.5
+16
+16
+12
+13
+0.001
40
Both inputs
N
+20
TYP
MAX
+V
REF
xk
+5.1
+0.1
+10
UNITS
AIN+ to AIN-, k = 5/4.096
AIN+ to GND
AIN- to GND
Acquisition phase
V
V
µA
pF
mA
Bits
Bits
LSB
µV/°C
LSB
ppm/°C
LSB
LSB
LSB
LSB
dB
dB
LSB
RMS
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Maxim Integrated
│
2
MAX11168
16-Bit, 500ksps, ±5V SAR ADC with
Internal Reference in µMAX
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25°C.) (Note 2)
PARAMETER
REFERENCE (Note 7)
REF Initial Accuracy
REF Temperature Coefficient
REF Output Impedance
DYNAMIC PERFORMANCE (Note 6)
Signal-to-Noise Ratio (Note 7)
Signal-to-Noise Plus Distortion
(Note 7)
Spurious-Free Dynamic Range
Total Harmonic Distortion
Intermodulation Distortion (Note 8)
SAMPLING DYNAMICS
Throughput Sample Rate
Transient Response
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
POWER SUPPLIES
Analog Supply Voltage
Interface Supply Voltage
Analog Supply Current
V
DD
Shutdown Current
Interface Supply Current (Note 9)
OVDD Shutdown Current
Power Dissipation
V
DD
= 5V, V
OVDD
= 3.3V
V
OVDD
= 2.3V
V
OVDD
= 5.25V
V
DD
V
OVDD
I
VDD
4.75
2.3
5.0
0.01
1.4
3.8
0.01
37.6
5.25
5.25
7.0
10
2.0
4.8
10
V
V
mA
µA
mA
µA
mW
Full-scale step
-3dB point
-0.1dB point
6
> 0.2
2.5
10
0.01
500
400
ksps
ns
MHz
ns
ps
RMS
SNR
SINAD
SFDR
THD
IMD
f
IN
= 10kHz
f
IN
= 10kHz
89.5
89.0
96
92.3
90.8
103
-101
-115
-96
dB
dB
dB
dB
dBFS
V
REF
TC
REF
Z
REF
4.092
4.096
±7
0.1
4.100
±17
V
ppm/°C
Ω
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
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Maxim Integrated
│
3
MAX11168
16-Bit, 500ksps, ±5V SAR ADC with
Internal Reference in µMAX
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
0.7 x
V
OVDD
0.3 x
V
OVDD
±0.05 x
V
OVDD
10
V
IN
= 0V or V
OVDD
-10
V
OVDD
- 0.4
0.4
-10
15
t
CYC
t
CONV
t
ACQ
t
CNVPW
t
SCLK
CNVST rising to data available
t
ACQ
= t
CYC
- t
CONV
CS
mode
V
OVDD
> 4.5V
SCLK Period (CS Mode)
V
OVDD
> 2.7V
V
OVDD
> 2.3V
V
OVDD
> 4.5V
SCLK Period (Daisy-Chain Mode)
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Valid
Delay
t
SCLK
t
SCLKL
t
SCLKH
V
OVDD
> 4.5V
t
DSDO
V
OVDD
> 2.7V
V
OVDD
> 2.3V
V
OVDD
> 2.7V
V
OVDD
> 2.3V
2
1.3
0.5
5
14
20
26
16
24
36
5
5
12
18
23
ns
ns
ns
ns
ns
1.5
+10
+10
TYP
MAX
UNITS
DIGITAL INPUTS (SDI, SCLK, CNVST)
Input Voltage High
Input Voltage Low
Input Hysteresis
Input Capacitance
Input Current
DIGITAL OUTPUT (SDO)
Output Voltage High
Output Voltage Low
Three-State Leakage Current
Three-State Output Capacitance
TIMING (Note 9)
Time Between Conversions
Conversion Time
Acquisition Time
CNVST Pulse Width
µs
µs
µs
ns
V
OH
V
OL
I
SOURCE
= 2mA
I
SINK
= 2mA
V
V
µA
pF
V
IH
V
IL
V
HYS
C
IN
I
IN
V
V
V
pF
µA
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Maxim Integrated
│
4
MAX11168
16-Bit, 500ksps, ±5V SAR ADC with
Internal Reference in µMAX
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25°C.) (Note 2)
PARAMETER
CNVST Low to SDO D15 MSB Valid
(CS Mode)
CNVST High or SDI High or Last
SCLK Falling Edge to SDO High
Impedance
SDI Valid Setup Time from CNVST
Rising Edge
SDI Valid Hold Time from SCLK
Rising Edge
SYMBOL
t
EN
t
DIS
t
SSDISCK
t
HSDISCK
V
OVDD
< 2.7V
CS
mode
CONDITIONS
V
OVDD
> 2.7V
MIN
TYP
MAX
14
17
20
UNITS
ns
ns
4-wire
CS
mode
4-wire
CS
mode
5
0
5
5
5
0
15
ns
ns
ns
ns
ns
ns
SCLK Valid Setup Time from CNVST
t
SSCKCNV
Daisy-chain mode
Rising Edge
SCLK Valid Hold Time from CNVST
Rising Edge
SDI Valid Setup Time from SCLK
Falling Edge
SDI Valid Hold Time from SCLK
Falling Edge
t
HSCKCNV
Daisy-chain mode
t
SSDISCK
t
HSDISCK
Daisy-chain mode
Daisy-chain mode
Daisy-chain mode with busy indicator,
V
OVDD
> 4.5V
Daisy-chain mode with busy indicator,
V
OVDD
> 2.3V
SDI High to SDO High
t
DSDOSDI
ns
26
Note 2:
Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25°C
and +85°C. Limits below +25°C are guaranteed by design and device characterization. Typical values are not guaranteed.
Note 3:
See the
Analog Inputs
and
Overvoltage Input Clamps
sections.
Note 4:
See the
Definitions
section.
Note 5:
Defined as the change in positive full-scale code transition caused by a ±5% variation in the V
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