USER’S MANUAL
HIP2103_4MBEVAL1Z
HIP2103, HIP2104 Evaluation Board
AN1896
Rev 0.00
November 13, 2013
The 6 position DIP switch is used to setup the PWM switching
frequency (positions 1, 2, and 3) and the dead-time (positions
4, 5, and 6). One specific combination of DIP switch settings
(all positions set to on) disables the signals from the
microcontroller and enables all of the external inputs.
For those customers who would like to modify the firmware of
the PIC18F2431 microcontroller, an RJ25 connector is
provided for easy connection with Microchip firmware
development tools (not provided or supported by Intersil).
Introduction
The HIP2103_4MBEVAL1Z is an evaluation tool for the
HIP2103 and HIP2104 half bridge MOSFET drivers. This tool
consists of a mother board and HIP2103DBEVAL1Z and
HIP2104DBEVAL1Z evaluation daughter cards. The mother
board platform provides an on-board microcontroller that is
used to generate appropriate control inputs to the HIP2103 or
HIP2104. The frequency, the PWM duty cycle, and the dead-time
provided by the microcontroller are user adjustable.
For customers who desire to provide their own external signals,
the on-board controller can be configured to allow the
daughter cards to be controlled by externally provided inputs.
The daughter cards can also be used as stand-alone units
mounted on a customer designed main board that
incorporates customer selected bridge FETs and any other
external circuits desired. The daughter cards have optional
circuits so that the HIP2103 or HIP2104 can be configured as
required by the customer’s application.
VCC and VDD on/off
(HIP2104 only)
DEAD FREQ
TIME
uC BIAS
OPTION
BRIDGE
BIAS
LOAD
EXTERNAL
INPUTS
Vdd, Vcc
I/O
BIAS
uC
Specifications
Bridge Bias Voltage (V
BAT
)
External Bias for Microcontroller 3.3V - 5.0V, ~30mA
Maximum Bridge Current
PWM Switching Frequency
PWM Duty Cycle
Dead-time
Large Terminal Blocks
Small Terminal Blocks
20A
5kHz to 40kHz in 5kHz increments
adjustable from 0% to ~ 98%
0.0µs to 2.8µs in 400ns increments
15A each connection
6A each connection
DUTY
CYCLE
Not used
5V minimum, 50V maximum
operating including transients
Scope
This application note covers the use of the HIP2103_4 mother
board and the HIP2103_4 daughter cards. Details for setting
up and using the microcontroller are covered. Assembly
options on the motherboard are also reviewed. Sample
waveforms are also provided.
The microcontroller firmware is provided on request but the
only support offered by Intersil will be for bug corrections.
Please refer to Microchip for details on the use of the
PIC18F2431.
Observe the
installation
polarity
Physical Layout
The HIP2103_4MBEVAL1Z board is 84mm by 94mm. The
tallest component is the RJ25 connector. The total height is
38mm. Multiple inputs have miniature terminal blocks and the
high current battery inputs and load outputs have larger
terminal blocks rated for 15A each connection. Three
push-buttons are used for RESET, START/STOP, and SLEEP
functions. An on-board potentiometer is used to adjust the
duty cycle.
FIGURE 1. HIP2103_4MBEVAL1Z, FRONT AND BACK VIEWS
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HIP2103_4MBEVAL1Z
Block Diagram
Optional external
LI, HI, VCen, and
Vden Inputs
application. The jumper strap option, J2, is used to select the
appropriate bias source labeled VCC from the HIP2104 or 5V
from an external bias connected to 5V and GND on TB8.
The 12V bias for the HIP2103 daughter card must be supplied by
an external source connected to VDD and GND of TB6.
An external 12V bias is not required for the HIP2104 daughter
card because VDD is provided internally by the HIP2104 driver.
Push
buttons
LEDs
MicroController and Associated Circuits
External Inputs
Buffer
Microcontroller
Ext.
Bias
Option
switches
VCen, Vden, LI,
HI, Multiplexer
The PWM frequency and the dead-time options of the
microcontroller are configured by the SW5 DIP switch. Refer to
the chart on the mother board schematic (page 9) for the DIP
switch settings or to Table 1. The DIP switch settings are read
only once after the Start/Stop button is pressed to start the
PWM. Any changes to the frequency or dead-time settings are
not recognized until the PWM is stopped then re-started.
Turning the potentiometer, R1, fully counter clockwise (CCW)
reduces the duty cycle of the output of the bridge to a minimum.
Turning fully clockwise results with a maximum duty cycle. The
duty cycle is proportional to the tap voltage of the potentiometer
independent of the PWM frequency. The dead-time subtracts
from the duty cycle period on the leading edge of the HI and LI
inputs to the daughter cards altering the actual duty cycle.
To emulate controllers that may to be used by customers that do
not have the ability to generate dead-time, the dead-time of the
microcontroller can be set to zero. On the daughter cards, an
optional RCD circuit is provided for the LI and HI inputs of the
HIP2103, HIP2104 to generate dead-time.
Be cautious if the
zero
dead-time option is selected when the
HIP2103, HIP2104 daughter cards are not configured for delays
with the RCD circuit as this will result with shoot-thru currents in
the bridge.
Four LEDs are used to indicate the operating status of the
microcontroller. Refer to the Setup and Operating Instructions
section for complete details.
Jumper
Option
3.3V
12V
HIP2103
or
HIP2104
Daughter Card
Half Bridge FETs
Optional
DC Motor or
other Loads
FIGURE 2. HIP2103_4MBEVAL1Z, BLOCK DIAGRAM
The HIP2103_4 evaluation board is a fully self contained test
platform to evaluation the HIP2103 or the HIP2104 which are
provided on daughter cards.
Half Bridge
The bridge is composed of two (SiR662DP) 60A, 60V, MOSFETs.
Each FET has an optional gate to source and drain to gate
capacitors to allow the emulation of FETs with larger
capacitances if desired. An optional series gate resistor is also
provided for each bridge FET that can also be used the emulate
the internal gate resistance. The current rating of these
SiR662DP MOSFETs was chosen primarily to eliminate the need
of a heat sink when operating with heavy current loads. The
maximum output load current is constrained by the current
rating of the VBAT (TB1) and the Vout (TB7) terminal blocks. If a
load current higher than 15A is desired, it is recommended that
the battery and load wires are soldered directly to the solder pads
of the TB1 and TB2 terminal blocks on the bottom of the PCB.
The bridge bias source is connected to the GND_VBAT terminal
block (TB1). The voltage source can be either a current limited
power supply (recommended for initial setup) or a battery (a fuse
is highly recommended).
An external load can be connected to the GND_VOUT (TB7)
terminal block. The load can be of any configuration (for example
Evaluation Board Application
The HIP2103_4MBEVAL1Z mother board and associated
daughter cards are the same test boards as used by the Intersil
application engineers and I.C. designers to evaluate the
performance of the HIP2103 and HIP2104 MOSFET drivers.
Bias Supplies
The HIP2103_4MBEVAL1Z mother board requires a current
limited lab supply (0V to 50V) for the VBAT and GND inputs on
TB1. The current capacity is dependant on the users desired load
if any.
An external 3.3V to 5V bias supply (~25mA) is required for the
microcontroller and associated circuits. Alternatively, the VCC
output of the HIP2104 daughter card can be used to provide the
3.3V bias for the microcontroller as intended in a real
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HIP2103_4MBEVAL1Z
a DC motor or an LCR load) as desired by the user within the
constraints of the bridge FETs and the terminal blocks.
Even though the FETs have a voltage rating of 60V, the maximum
operating voltage is limited to 50V by the rating of the HS and
VBAT pins on the HIP2103, HIP2104 drivers.
R23
D1
2
0
1
SW4
3
1
C8
S1B
2.2UF
2
VCEN SWITCH
Daughter Cards
Two different daughter cards are provided for evaluation. These
cards are mounted on the back side of the mother board to
facilitate temperature testing using a temperature forcing system.
The HIP2103DBEVAL1Z and HIP2104DBEVAL1Z daughter cards
are identical except for the differences between the HIP2103
and the HIP2104.
The HIP2104 has integrated LDOs for the VDD bias of the driver
and VCC for the bias of the controller. VDD and VCC outputs of the
HIP2104 are available on the GND_VDD_VCC terminal block
(TB6). External loads on the LDOs can be connected here.
When using the HIP2103 daughter card, both VDD and VCC must
come from external sources. The same terminal block used for
the LDO outputs of the HIP2104 can be used as external inputs
when using the HIP2103.
As mentioned previously, the J2 strap option is used to select the
bias source for the microcontroller. If the 5V strap option is
selected, the bias to the microcontroller will always be present (if
the external source is on) even when the LDO outputs of the
HIP2104 are not enabled. This is desirable during the initial
setup of the evaluation board or when testing the HIP2103.
11
SW3
3
R33
1
VDEN SWICH
100
2
GND1
VCEN
VDEN
HI-IN
LI-IN
VDD
VCC
1
DAUG
S
SK2
SK2
SK2
SK2
SK2
SK2
R30
U3
2
1
1
3
1
D2
3
3
100
2
3
4
5
6
7
U3
D3
FIGURE 3. DIODE TO SUPPRESS LI-ON BATTERY RIPPLE
• Gate to source resistors on the bridge FETs. (R19 and R21 are
omitted)
• Series connected gate resistors on each bridge FETs (R34 and
R35 are installed with zero ohms)
• Gate to source, and gate to drain capacitor on the bridge FETs
(C11, C12, C9, and C10 omitted). The capacitors can be added
to emulate larger FETs.
VBAT
C11
The VCEN and VDEN inputs of the HIP2104, are used to enable
the LDO outputs of the HIP2104. These two signals are provided
by two mechanical switches, SW2 and SW3. Mechanical
switches are used to demonstrate the intended use of the VCEN
and VCEN inputs of the HIP2104 although digital logic signals
can also be used when external inputs are optionally chosen. The
debouncing feature of the VDCEN and VDEN inputs can also be
observed when using the mechanical switches. Note that either
of these two switches can be turned on or off randomly to
demonstrate the performance of the HIP2104 when either of the
LDO outputs are turned off during operation of the bridge.
Three push buttons provide control signals to the microcontroller.
As usual, the reset button restarts the firmware. The Start/Stop
button starts and stops the PWM signals to the LI and HI inputs
of the HIP2103, HIP2104. The Sleep button turns on and off the
sleep mode.
R34
4
Q1
1
2
3
OPEN
OPEN
C9
R19
0
SI7430DP
0.1UF
OUT
10UF
10UF
C13
C14
C15
Switches and Push Buttons
OPEN
5
6
7
8
C12
R35
VOUT
VOUT
GND
OPEN
SI7430DP
5
6
7
8
4
2
1
OPEN
OPEN
0
C10
Q2
1
2
3
R21
TB7
FIGURE 4. OPTIONAL RESISTORS AND CAPACITORS FOR
BRIDGE FETs
User Assembly Options
The following user optional assembly features are provided on
the evaluation mother board:
• Series connected diode (D1) on the VBAT input to the HIP2104
daughter card for holding up VBAT when there is severe ripple
voltage from a LI-ON battery. A zero ohm resistor (R23) shorts
out this diode when not required (installed)
The following user optional assembly features are provided on
the HIP2103, HIP2104 daughter cards.
• The HO and LO outputs have options for a bypass diode across
a series connected gate resistor for slower turn-on and faster
turn-off of the driven bridge FET. The default configuration
includes the bypass diode in parallel with a 24.9Ω resistor.
AN1896 Rev 0.00
November 13, 2013
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HIP2103_4MBEVAL1Z
1
2
3
J1
J1
J1
GND
VBAT
HB
HI-OUT
HS-OUT
LO-OUT
GND
GND
GND
VBAT
HB
HO
12
11
10
9
8
7
HB
HS
HO
LO
1
2
3
J1
J1
J1
C5
1
D3
2
C5
1
D3
2
1UF
R6
4
HS
LO
VSS
S)
RAANZ
RTAANZ
2.2UF
OPEN
OPEN
24.9
R5
C9
R7
J1
J1
J1
HO
HS
LO
C6
C7
C8
R3
0.1UF
R6
4
24.9
R5
C9
R7
J1
J1
J1
5
6
0
2
5
6
24.9
0
2
OPEN
OPEN
1
D4
GND2
7
8
9
J1
J1
J1
24.9
OPEN
1
D4
GND2
7
8
9
FIGURE 7. RC FILTER ON HS PIN (NOT REQUIRED)
J1
J1
J1
Switching Transients
The recommended maximum operating voltage on the HS, VBAT,
VCEN, and VDEN pins is 50V. This includes the switching transients
resulting from parasitic inductance in the bridge circuit.
In the case of the VCEN and VDEN inputs, the parasitic inductance
resulting from the leads to and from the mechanical switches will
resonate with the input capacitance of these pins and with the
paralleled external parasitic capacitance on the PCB. When
operating at higher voltage levels, it is necessary to have series
connected resistor, R30 and R33 (on the mother board), to
dampen the ringing spike. By default, R30 and R33 are 100Ω.
FIGURE 5. BYPASS DIODES (D3, D4) FOR SLOW TURN-ON AND
FAST TURN-OFF
• The LI and HI inputs have optional RCD circuits for the purpose
of generating dead-time if a controller is used that does not
have built-in dead-time capability. As previously mentioned,
the on-board microcontroller can be configured for no
dead-time delays. The default configuration includes Schottky
diodes in parallel with a zero ohm resistor.
LI
J2
J2
J2
J2
J2
J2
J2
1
2
3
4
5
6
7
1
1
1
2
3
HI
VDD
VCC
R23
D1
0
C8
S1B
2.2UF
U
VDEN
VCEN
VCC
VDD
HI
11
2
1
SW4
2
3
1
VCEN SWITCH
SW3
3
R33
1
VDEN SWICH
2
4
R30
2
R2
R1
GND1
8
9
0
1
4.7UF
OPEN
OPEN
1UF
0
C1
HI
LI
C2
C3
C4
5
6
13
100
D1
GND1
VCEN
VDEN
HI-IN
VDD
VCC
D2
100
LI-IN
2
1
1
3
1
DAUG
S
SK2
SK2
SK2
SK2
SK2
SK2
LI
EP(V
HIP2104
HIP2104
U3
2
D2
3
3
2
3
4
5
6
U3
D3
J2
J2
FIGURE 8. VCEN AND VDEN DAMPENING RESISTORS
7
FIGURE 6. BYPASS DIODES (D1, D2) USED FOR DEAD TIME
GENERATION
• The HS pin has an RC filter (R7/C7 on the HIP2103 daughter
card and R7/C9 on the HIP2104 daughter card) that was
required for early engineering samples (rev. A) of the
HIP2103/4. This filter is not necessary for the production
grade parts. The default value for R7 is zero ohms and the
capacitor between HS and VSS is omitted.
A similar transient situation may occur with the HS pin. In this
situation, a ringing spike can be more severe because of high
speed switching from the bridge FETs, the large amplitude of
switching currents, and because of parasitic inductance
associated with the bridge high current PCB traces. Because the
amplitude of the ringing spike also increases with the switching
load current amplitude, evaluation should be over the full
operating load range including fault currents. Good bridge circuit
PCB design will minimize but cannot totally eliminate ringing on
the HS node.
These switching transients are relatively fast. When evaluating the
spikes on these pins, it is necessary to use a time base on the scope
of about 100ns/division. Slower sweep speeds may mask the
switching spike depending on the sample rate of the digital scope.
AN1896 Rev 0.00
November 13, 2013
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HIP2103_4MBEVAL1Z
Other methods can also be used to reduce ringing on the HS
node. Sufficiently large value gate resistors on the bridge FETs
will reduce the switching speed and consequently the amplitude
of the ringing. The above mentioned RC filter on the HS pin can
also be used to attenuate the spike directly on the HS pin. By
default, the gate resistors on the HIP2103/4 daughter cards, R5
and R6, is 24.9Ω. With this evaluation PCB layout, 24.9Ω is
sufficient to prevent excessive switching transient but a
customer’s PCB layout may require more or less gate resistance
or another method to attenuate the switching transients.
Another source of switching transients that must be dealt with is
from the bridge voltage source, especially with LI-ON batteries.
When the LI_ON battery load current is interrupted when the
bridge turns off, the voltage from the battery can rise
dramatically because of the internal inductance of the battery.
The usual solution is to have sufficiently large capacitance across
the bridge. This bridge bypass capacitor is effectively an LC filter
working with the internal inductance of the LI-ON battery
(typically a few hundred nH). If the capacitor value is large
enough, the battery voltage will be close to the nominal unloaded
value with minimal ripple. Another approach to reduce the
amplitude of the voltage transient from the battery without
increasing the size or value of the bridge capacitor is to increase
the PWM switching frequency.
If it is not desirable to use relatively large value capacitors across
the bridge, a clamping method must be used to limit the peak
voltage ripple from the battery. In any case, a relatively small
capacitor across the bridge should be used to limit the rate of
change of the ripple voltage and to minimize the effects of the
PCB parasitic trace inductance on the HS pin.
Another consequence of allowing a relatively large ripple voltage
on the battery is that under heavy load conditions, the voltage
ripple valley will drop to very low levels. Because most motor
loads respond to the average voltage applied, this ripple voltage
is of minimal concern. The problem is that if the valley voltage
drops too low, the 12V LDO (VDD) of the HIP2104 will sag
resulting with a lower gate drive voltage. The UVLO of the
HIP2103/4 is 4.5V (or optionally 7.5V). If the bridge FETs are
selected appropriately, this low gate drive voltage will have not
significant effect except for the usual consequence of higher
r
DS(ON)
of the bridge FETs.
To mitigate this problem of excessively low ripple voltage from
the battery, a diode in series with the VBAT input of the HIP2104
daughter card with a capacitor to ground will hold up the voltage
on VBAT (and consequently the VCC and VDD outputs) when the
valley voltage is low (Figure 3). This series connected diode is an
assembly option on the HIP2103_4MBEVAL1Z mother board.
The default configuration has a zero ohm resistor in parallel with
the diode.
for testing (if any). If no load is applied, 200mA is sufficient. If
a battery is the power source, it is highly recommended that an
appropriate fuse be used. With a LI-ON battery, it is necessary
to add sufficient capacitance (100µF or greater) across the
VBAT terminal block to prevent excessive ringing.
• Bias supply, 12V at ~50mA, require for testing the HIP2103
• Bias supply, 3.3V to 5.0V at ~50mA, for testing the HIP2103
• Bench fan (only necessary when testing with large loads at
elevated ambient temperatures)
• Four channel oscilloscope, ~500MHz recommended
• Current Probe (optional) when testing with external loads.
• Multimeter
Initial Configuration for the Microcontroller
The following procedure illustrates how to configure the
microcontroller without applying power to the bridge.
1. Connect a 5.0V bias supply to the +5V_GND terminal block
(TB8). This voltage powers the microcontroller.
2. Ensure that the jumper strap on J2 is on the 5V option. This
will connect the microcontroller to the external lab supply.
3. Setup the DIP switch on the mother board with the desired
PWM frequency and dead-time. For the initial setup, start with
20kHz and 400ns dead-time (in bold type).
TABLE 1. DIP SWITCH OPTIONS
SWITCH POSITION
6
x
x
x
PWM Frequency
x
x
x
x
x
External inputs
1
0
0
0
Dead-Time
0
1
1
1
1
5
x
x
x
x
x
x
x
x
1
0
0
1
1
0
0
1
1
4
x
x
x
x
x
x
x
x
1
0
1
0
1
0
1
0
1
3
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x
x
x
2
0
0
1
1
0
0
1
1
1
x
x
x
x
x
x
x
x
1
0
1
0
1
0
1
0
1
1
x
x
x
x
x
x
x
x
0.000µs
0.400µs
0.800µs
1.200µs
1.600µs
2.000µs
2.400µs
2.800µs
5kHz
10kHz
15kHz
20kHz
25kHz
30kHz
35kHz
40kHz
Setup and Operating Instructions
The follow procedure ensures a correct setup of the evaluation
board and illustrates various operating methods.
Required Lab Equipment
• Power supply (or battery), 13V minimum to 50V maximum
operating for the bridge bias. The current rating of the power
supply must have sufficient capacity for the external load used
4. Connect scope probes on the HI and LI test points on the
mother board. Set the time base to 200ns/Div. Set the
vertical gain to 2V/Div. Set the trigger on the LI input at the
2.5V level with a negative edge trigger. Set the trigger position
at the 400ns division (on the left side of the screen) and use
the auto trigger mode.
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