IDT74ALVCHR162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
BUS TRANSCIEVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVCHR162245
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
APPLICATIONS:
• Balanced Output Drivers: ±12mA
• Low Switching Noise
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. The ALVCHR162245 device is designed for asynchronous
communication between data buses. The control-function implementation
minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit
transceiver. It allows data transmission from the A bus to the B bus or from
the B bus to the A bus, depending on the logic level at the direction control
(DIR) input. The output-enable (OE) input can be used to disable the
device so that the buses are effectively isolated.
The ALVCHR162245 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
The ALVCHR162245 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1
DIR
1
2
DIR
48
24
25
36
13
35
14
33
16
32
17
30
19
29
20
1
O E
2
A
1
2
OE
1
A
1
47
2
46
3
44
5
43
6
41
8
40
9
38
11
1
B
1
2
A
2
1
B
2
2
A
3
1
B
3
2
A
4
1
B
4
2
A
5
1
B
5
2
A
6
1
B
6
2
A
7
27
1
B
7
2
A
8
26
2
B
1
1
A
2
2
B
2
1
A
3
2
B
3
1
A
4
2
B
4
1
A
5
2
B
5
1
A
6
2
B
6
1
A
7
22
2
B
7
1
A
8
37
12
1
B
8
23
2
B
8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4606/1
IDT74ALVCHR162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
DIR
1
B
1
1
B
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
(2)
Terminal Voltage with Respect to GND
–0.5 to +4.6
–65 to +150
–50 to +50
±50
–50
±100
Unit
V
V
°C
mA
mA
mA
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
OE
1
A
1
1
A
2
V
TERM
(3)
Terminal Voltage with Respect to GND –0.5 to V
CC
+0.5
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
GND
1
B
3
1
B
4
GND
1
A
3
1
A
4
V
CC
1
B
5
1
B
6
V
CC
1
A
5
1
A
6
GND
1
B
7
1
B
8
2
B
1
2
B
2
GND
1
A
7
1
A
8
2
A
1
2
A
2
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
(T
A
= +25°C, F = 1.0MHz)
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
GND
2
B
3
2
B
4
GND
2
A
3
2
A
4
Output Capacitance
I/O Port Capacitance
NOTE:
1. As applicable to the device type.
V
CC
2
B
5
2
B
6
V
CC
2
A
5
2
A
6
PIN DESCRIPTION
Pin Names
xOE
DIR
xAx
(1)
xBx
(1)
Description
Output Enable Inputs (Active LOW)
Direction Control Inputs
Side A Inputs or 3-State Outputs
Side B Inputs or 3-State Outputs
GND
2
B
7
2
B
8
2
DIR
GND
2
A
7
2
A
8
2
OE
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
SSOP/ TSSOP/ TVSOP
TOP VIEW
FUNCTION TABLE
Inputs
xOE
L
L
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
(EACH 8-BIT SECTION)
(1)
xDIR
L
H
X
Outputs
Bus B data to A bus
Bus A data to B bus
High Z State
2
IDT74ALVCHR162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
40
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
±500
Unit
µA
µA
µA
3
IDT74ALVCHR162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 6mA
I
OH
= – 4mA
I
OH
= – 8mA
I
OH
= – 6mA
I
OH
= – 12mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 4mA
I
OL
= 8mA
I
OL
= 6mA
I
OL
= 12mA
Min.
V
CC
– 0.2
1.9
1.7
2.2
2
2.4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range. T
A
= –
40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
24
4
V
CC
= 3.3V ± 0.3V
Typical
32
5
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK
(o)
Parameter
Propagation Delay
xAx to xBx or xBx to xAx
Output Enable Time
xOE to xAx or xBx
Output Disable Time
xOE to xAx or xBx
Output Skew
(2)
1
6.3
1
6.8
Min.
1
Max.
4.9
Min.
V
CC
= 2.7V
Max.
4.7
6.7
5.7
V
CC
= 3.3V ± 0.3V
Min.
1
1
1
Max.
4.2
5.6
5.5
500
Unit
ns
ns
ns
ps
—
—
—
—
—
—
—
—
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCHR162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALVC Link
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
500
Ω
Pulse
Generator
(1, 2)
SAME PHASE
INPUT TRANSITION
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
V
LOAD
Open
GND
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
6
2.7
1.5
300
300
50
t
PHL
Propagation Delay
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
LZ
V
OL
V
OH
V
HZ
0V
ALVC Link
V
IN
D.U.T.
V
OUT
R
T
500
Ω
C
L
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
V
IH
INPUT
V
T
0V
V
OH
OUTPUT 1
V
T
V
OL
V
OH
OUTPUT 2
t
PLH2
t
PHL2
ALVC Link
t
SU
t
H
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Link
Set-up, Hold, and Release Times
t
PLH1
t
PHL1
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
T
ALVC Link
Pulse Width
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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