KH231
Fast Settling, Wideband Buffer/Amplifier (Av = ±1 to ±5)
Features
s
s
s
s
s
s
General Description
The KH231 Buffer/Amplifier is a wideband operational
amplifier designed specifically for high-speed, low-
gain applications. The KH231 is based on a current
feedback op amp topology-a unique design that both
eliminates the gain-bandwidth tradeoff and permits
unprecedented high-speed performance. (See table below.)
The KH231 Buffer/Amplifier is the ideal design alter-
native to low precision open-loop buffers and oscillation-
prone conventional op amps. The KH231 offers precise
gains from ±1.000 to ±-5.000 and linearity that is a
true 0.1%-even for demanding 50Ω loads. Open-loop
buffers, on the other hand, offer a nominal gain of
0.95 ±0.03 and a linearity of only 3% for typical loads.
A buffer’s settling time may look impressive but it is
usually specified at unrealistically large load resis-
tances or when the effects of thermal tail are not
included; the KH231 Buffer/Amplifier settles to 0.05%
in 15ns-while driving a 100Ω load.
Offsets and drifts, usually a low priority in conven-
tional high-speed op amp designs, were not ignored
in the KH231; the input offset voltage is typically 1mV
and input offset voltage drift is only 10µV/°C. The
KH231 is stable and oscillation-free across the entire
gain range and since it’s internally compensated, the
user is saved the trouble of designing external com-
pensation networks and having to “tweak” them in
production. The absence of a gain-bandwidth trade-
off in the KH231 allows performance to be predicted
easily; the table below shows how the bandwidth is
affected very little by changing the gain setting.
The KH231 is constructed using thin film resistor/bipolar
transistor technology, and is available in the following
versions:
The KH231 is constructed using thin film resistor/bipolar
transistor technology, and available in these versions:
KH231AI
KH231AK
KH231AM
-2
-5
Units
MHz
ns
V/ns
ns
165MHz closed-loop – -3dB bandwidth
15ns settling to 0.05%
1mV input offset voltage, 10µV/°C drift
100mA output current
Excellent AC and DC linearity
Direct replacement for CLC231
Applications
s
s
s
s
Driving flash A/D converters
Precision line driving
(a gain of 2 cancels matched-line losses)
DAC current-to-voltage conversion
Low-power, high-speed applications (50mW @ ±5V)
Small Signal Pulse Response
Output Voltage (400mV/div)
A
v
= 2
A
v
= -2
Time (5ns/div)
Bottom View
I
CC
Adjust
Case
ground
GND
7
Adjust -V
CC
8
9
-V
CC
V+ 6
10
K
Supply
Voltage
Non-Inverting
Input
Inverting
Input
Not
Connected
Collector
Supply
Output
+
V- 5
NC 4
3
Case
ground
GND
2
4
4
-
11 V
o
12
+V
CC
Collector
Supply
1
Supply
Voltage
Adjust +V
CC
I
CC
Adjust
Pins 2 and 8 are used to adjust the supply current or to adjust the off-
set voltage (see text). These pins are normally left unconnected.
-25°C to +85°C
-55°C to +125°C
-55°C to +125°C
Typical Performance
Gain Setting
Parameter
1
2
5
-1
-3dB bandwidth
180 165 130
rise time (2V)
1.8 2.0 2.5
slew rate
2.5 3.0 3.0
settling time (to 0.1%) 12 12 12
165 150 115
2.0 2.2 2.9
3.0 3.0 3.0
12 12 15
KH231HXC
KH231HXA
-55°C to +125°C
-55°C to +125°C
12-pin TO-8 can
12-pin TO-8 can, features
burn-in & hermetic testing
12-pin TO-8 can,
environmentally
screened and electrically
tested to MIL-STD-883
SMD#: 5962-8959401HXC
SMD#: 5962-8959401HXA
REV. 1A January 2004
DATA SHEET
KH231
KH231 Electrical Characteristics
(T
A
= +25°C, A
v
= +2V, V
CC
= ±15V, R
L
= 100Ω, R
f
= 250Ω; unless specified)
PARAMETERS
Ambient Temperature
Ambient Temperature
FREQUENCY DOMAIN RESPONSE
¦
-3dB bandwidth (note 2)
large-signal bandwidth
gain flatness (note 2)
¦
peaking
¦
peaking
¦
rolloff
group delay
linear phase deviation
reverse isolation
non-inverting
inverting
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
to 0.1%
overshoot
slew rate (overdriven input)
overload recovery
<50ns pulse, 200% overdrive
CONDITIONS
KH231AI
KH231AK/AM/HXC/HXA
V
o
≤2V
pp
V
o
≤10V
pp
V
o
≤2V
pp
0.1 to 50MHz
>50MHz
at 100MHz
to 100MHz
to 100MHz
TYP
+25°C
+25°C
165
95
0.1
0.1
0.4
3.5 ± 0.5
0.5
53
36
2V step
10V step
5V step
2.5V step
5V step
<1% error
120
-55
-59
-153
70
1
10
5.0
50
10
125
50
46
18
400
1.3
5, 37
±12
–
<-47
<-47
<-150
<100
<4.0
<25
<29
<125
<31
<200
>45
>40
<22
>100
<2.5
–
>±11
–
<-47
<-47
<-150
<100
<2.0
<25
<21
<125
<15
<200
>45
>40
<22
>200
<2.5
–
>±11
–
<-47
<-47
<-150
<100
<4.5
<25
<31
<125
< 35
<200
>45
>40
<22
>400
<2.5
–
>±11
ns
dBc
dBc
dBm(1Hz)
µVrms
mV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
kΩ
pF
Ω,
nH
V
OR
HD2
HD3
SNF
INV
VIO
DVIO
IBN
DIBN
IBI
DIBI
PSRR
CMRR
ICC
RIN
CIN
RO
VO
2.0
5.0
15
12
5
3.0
MIN & MAX RATINGS
-25°C
-55°C
>145
>80
<0.6
<1.5
<0.6
–
<2.0
>43
>26
<2.4
<7.0
–
<22
<15
>2.5
+25°C
+25°C
>145
>80
<0.3
<0.3
<0.6
–
<2.0
>43
>26
<2.3
<6.5
–
<17
<10
>2.5
+85°C
+125°C
>120
>60
<0.6
<0.8
<1.0
–
<2.0
>43
>26
<2.7
<6.5
–
<22
<15
>1.8
MHz
MHz
dB
dB
dB
ns
°
dB
dB
ns
ns
ns
ns
%
V/ns
SSBW
FPBW
GFPL
GFPH
GFR
GD
LPD
RINI
RIIN
TRS
TRL
TS
TSP
OS
SR
UNITS
SYM
NOISE AND DISTORTION RESPONSE
¦
2nd harmonic distortion
0dBm, 20MHz
¦
3rd harmonic distortion
0dBm, 20MHz
equivalent input noise
noise floor
>5MHz
integrated noise
5MHz to 200MHz
STATIC, DC PERFORMANCE
* input offset voltage
average temperature coefficient
* input bias current
average temperature coefficient
* input bias current
average temperature coefficient
* power supply rejection ratio
common mode rejection ratio
* supply current
MISCELLANEOUS PERFORMANCE
non-inverting input resistance
non-inverting input capacitance
output impedance
output voltage range
non-inverting
inverting
no load
DC
@ 100MHz
no load
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
V
CC
I
o
common mode input voltage, V
o
differential input voltage
thermal resistance
junction temperature
operating temperature
storage temperature
lead temperature (soldering 10s)
note 1:
*
¦
±20V
±100mA
(see V
cm
and V
o
limits plot on page 3)
±3V
(see thermal model)
+175°C
AI: -25°C to +85°C
AK/AM: -55°C to +125°C
-65°C to +150°C
+300°C
Recommended Operating Conditions
V
CC
I
o
common mode input voltage
gain range
note 3:
±5V to ±15V
±75mA
±(|V
CC
| -5)V
±1 to ±5
note 4:
note 2:
AI/AK/AM/HXC/HXA 100% tested at +25°C
AK/AM/HXC/HXA
100% tested at +25°C and sample
tested at -55°C and +125°C
¦
AI
sample tested at +25°C
The output amplitude used in testing is 0.63V
pp
. Performance
is guaranteed for conditions listed.
In the noninverting configuration, care should be taken when
choosing R
i
, the input impedance setting resistor; bias
currents of typically 5µA but as high as 24µA can create an
input signal large enough to cause overload. It is therefore
recommended that R
i
< (V
CC
/A
v
)/24µA.
These ratings protect against damage to the input stage
caused by saturation of either the input or output stages at
lower supply voltages, and against exceeding transistor
collector-emitter breakdown ratings at high supply voltages.
V
out(max)
is calculated by assuming no output saturation.
Saturation is allowed to occur up to this calculated level of
V
out
. V
cm
is defined as the voltage at the non-inverting
input, pin 6.
REV. 1A January 2004
2
KH231
DATA SHEET
KH231 Typical Performance Characteristics
(T
Non-Inverting Frequency Response
Normalized Magnitude (1dB/div)
Normalized Magnitude (1dB/div)
Gain
A
v
= 2
Gain
A
= +25°C, A
v
= +2, V
CC
= ±15V, R
L
= 100Ω, R
f
= 250Ω; unless specified)
Broadband Gain and Phase
Gain
A
v
= 2
Inverting Frequency Response
Magnitude (10dB/div)
A
v
= -2
Phase (180 deg/div)
Phase (45 deg/div)
Phase (45 deg/div)
A
v
= 5
A
v
= 1
Phase
A
v
= 5
A
v
= 2
A
v
= 1
A
v
= -5
Phase
A
v
= -5
A
v
= -2
A
v
= -1
A
v
= -1
Phase
0
100
200
0
100
200
0
500
1000
Frequency (MHz)
Bandwidth vs. V
CC
1.2
A
v
= 2
Frequency (MHz)
Frequency (MHz)
K
Frequency Response vs. R
L
K
Full Power Gain vs. Frequency
K
A
v
= 2
V
o
= 10V
pp
R
L
= 1K
Inverting
Relative Bandwidth
1.0
(1dB/div)
(1dB/div)
Pins 1 and 2 Shorted
Pins 8 and 9 shorted
R
L
= 200
R
L
= 50
Non-Inverting
0.8
0.6
R
L
= 100
0.4
4
6
8
10
12
14
16
0
125
250
0
100
200
±V
CC
(V)
130
Frequency (MHz)
50
Frequency (MHz)
Equivalent Input Noise
100
Inverting Current 23.8pA/√Hz
2nd and 3rd Harmonic Distortion Intercept
K
Intercept Point (+dBm)
2-Tone, 3rd Order Intermod. Intercept
K
A
v
= 2
K
100
Noise Voltage (nV/√Hz)
Intercept Point (+dBm)
110
90
70
50
30
1k
2nd harmonic intercept
exceeds +120dBm
below 350KHz
45
40
35
30
25
20
Noise Current (pA/√Hz)
I
2
10
Non-Inverting Current 2.5pA/√Hz
10
3rd harmonic intercept
exceeds +65dBm
below 350KHz
I
3
Voltage 2.8nV/√Hz
1
0
20
40
60
80
100
100
1k
10k
100k
1M
10M
10k
100k
1M
10M
100M
1
100M
Frequency (Hz)
Small Signal Pulse Response
Output Voltage (400mV/div)
Frequency (MHz)
Frequency (Hz)
K
Output Voltage (2V/div)
Large Signal Pulse Response
K
0.20
0.15
Settling Time
K
Settling Error (%)
A
v
= 2
A
v
= 2
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
5ns/div
50ns/div
A
v
= -2
A
v
= -2
Time (5ns/div)
CMRR and PSRR
K
Time (5ns/div)
Time (ns)
V
cm
K
V
o
Voltage Limits
and
20
|V
out
| max
|V
cm
| max
K
PSRR
50
PSRR/CMRR (dB)
CMRR
40
30
20
10
Indicated Voltage
15
|V
out
| max
10
note 4
on page 2
5
|V
cm
| max
0
1
10
100
1k
10k
100k
1M
10M 100M
0
5
10
15
20
Frequency (Hz)
|±V
CC
| (V)
K
REV. 1A January 2004
K
3
DATA SHEET
KH231
Operation
The KH231 Buffer/Amplifier is based on the current feed-
back op amp topology, a design that uses current feed-
back instead of the usual voltage feedback.
The use of the KH231 is basically the same as that of the
conventional op amp (see Figures 1 and 2). Since the
device is designed specifically for low gain applications,
the best performance is obtained when the circuit is used
at gains between ±1 and ±5. Additionally, performance is
optimum when a 250Ω feedback resistor is used.
type pc boards and methods. Sockets with small, short
pin receptacles may be used with minimal performance
degradation although their use is not recommended.
During pc board layout keep all traces short and direct
The resistive body of R
g
should be as close as possible
to pin 5 to minimize capacitance at that point. For the
same reason, remove ground plane from the vicinity of
pins 5 and 6. In other areas, use as much ground plane
as possible on one side of the board. It is especially
important to provide a ground return path for current from
the load resistor to the power supply bypass capacitors.
Ceramic capacitors of 0.01 to 0.1µf (with short leads)
should be less than 0.15 inches from pins 1 and 9.
Larger tantalum capacitors should be placed within one
inch of these pins. V
CC
connections to pins 10 and 12
can be made directly from pins 9 and 1, but better supply
rejection and settling time are obtained if they are
separately bypassed as in figures 1 and 2. To prevent
signal distortion caused by reflections from impedance
mismatches, use terminated microstrip or coaxial cable
when the signal must traverse more than a few inches.
Since the pc board forms such an important part of the
circuit, much time can be saved if prototype boards of
any high frequency sections are built and tested early in
the design phase. Evaluation boards designed for either
inverting or non-inverting gains are available.
Distortion and Noise
The graphs of intercept point, I
2
and I
3
, versus
frequency on the preceding page make it easy to predict
the distortion at any frequency given the output voltage of
the KH231. First, convert the output voltage (V
o
) to V
rms
= (V
pp
/2√2) and then to P = [(10log
10
(20V
rms
2
)] to get the
power output in dBm. At the frequency of interest, its 2nd
harmonic will be S
2
= (I
2
-P)dB below the level of P. Its
third harmonic will be S
3
= 2(I
3
- P)dB below P, as will the
two-tone third order intermodulation products. These
approximations are useful for P < -1dB compression levels.
Approximate noise figure can be determined for the
KH231 using the equivalent input noise graph on the
preceding page. The following equation can be used to
determine noise figure (F) in dB.
2
i
n
R
f 2
2
V
n
+
A
v2
F
=
10log
1
+
4kTR
s
∆
f
+15V
3.9
33Ω
0.1
6
1
12
11
10
3,7
9
.01
Capactance in
µF
V
in
R
i
49.9Ω
R
g
+
-
KH231
5
V
o
250Ω
R
L
100Ω
-15V
3.9
33Ω
0.1
.01
A
v
=
1+
R
f
R
g
R
f
= 250Ω
Figure 1: Recommended non-inverting gain circuit
+15V
3.9
33Ω
0.1
100Ω
R
g
6
1
12
11
10
3,7
9
.01
Capactance in
µF
+
-
KH231
5
V
o
250Ω
R
L
100Ω
V
in
R
i
-15V
3.9
33Ω
0.1
.01
R
f
A
v
= −
R
g
R
f
= 250Ω
For Z
in
= 50Ω, select
R
g
|| R
i
= 50Ω
Figure 2: Recommended inverting gain circuit
Layout Considerations
To assure optimum performance the user should follow
good layout practices which minimize the unwanted
coupling of signals between nodes. During initial bread-
boarding of the circuit use direct point to point wiring,
keeping the lead lengths to less than 0.25”. The use of
solid, unbroken ground plane is helpful. Avoid wire-wrap
4
Where V
n
is the rms noise voltage and i
n
is the rms noise
current. Beyond the breakpoint of the curves (i.e., where
they are flat), broadband noise figure equals spot noise fig-
ure, so
∆f
should equal one (1) and V
n
and i
n
should be
read directly off the graph. Below the breakpoint, the noise
must be integrated and
∆f
set to the appropriate bandwidth.
REV. 1A January 2004
KH231
DATA SHEET
Offset Voltage Adjustment
If trimming of the input offset voltage (V
os
= V
ni
-V
in
) is
desired, a resistor value of 10kΩ to 1MΩ placed between
pins 8 and 9 will cause V
os
to become more negative by
8mV to 0.2mV respectively. Similarly, a resistor placed
between pins 1 and 2 will cause V
os
, to become more
positive.
Thermal Considerations
At high ambient temperatures or large internal power
dissipations, heat sinking is required to maintain
acceptable junction temperatures. Use the thermal
model on the previous page to determine junction
temperatures. Many styles of heat sinks are available for
TO-8 packages; the Thermalloy 2240 and 2268 are good
examples. Some heat sinks are the radial fin type which
cover the pc board and may interfere with external
components. An excellent solution to this problem is to
use surface mounted resistors and capacitors. They
have a very low profile and actually improve high
frequency performance. For use of these heat sinks with
conventional components, a 0.1” high spacer can be inserted
under the TO-8 package to allow sufficient clearance.
T
case
100°C/W
T
j(pnp)
P
pnp
100°C/W
T
j(npn)
P
npn
17.5
°
C/W
T
j(circuit)
P
circuit
+
-
T
ambient
θ
ca
θ
ca
= 65°C/W for the KH231 without heat sink in still air.
30°C/W for the KH231 with a Wakefield 215 heat
sink in still air.
10°C/W for the KH231 with a Wakefield 215 heat
sink at 300 ft/min air.
30°C/W for the KH231 with a Thermalloy 2240A
heat sink in still air.
5°C/W for the KH231 with a Thermalloy 2240A
heat sink at 500 ft/min air.
For example, with the KH231 operating at ±15V while
driving a 100Ω load at 15V
pp
output (50% duty cycle
pulse waveform, DC = 0), P
(npn)
= P
(pnp)
= 190mW (R
col
= 33) and P
(cir)
= 0.48W. Then with the Wakefield
215 heat sink and air flow of 300 ft/min the output
transistors’ T
j
is 28°C above ambient and worst case T
j
in
the rest of the circuit is 32°C above ambient. In still air,
however, the rise in T
j
is 45°C and 49°C, respectively.
With no heat sink, the rise in T
j
is 75°C and 79°C,
respectively! Under most conditions,
HEAT SINKING IS
REQUIRED.
Other methods of heat sinking may be used, but for
best results, make contact with the base of the KH231
package, use a large thermal capacity heat sink and use
forced air convection.
Low V
CC
Operation: Supply Current Adjustment
The KH231 is designed to operate on supplies as low as
±5V. In order to improve full bandwidth at reduced sup-
ply voltages, the supply current (I
CC
) must be increased.
The plot of Bandwidth vs. V
CC
, shows the effect of short-
ing pins 1 and 2 and pins 8 and 9; this will increase both
bandwidth and supply current. Care should be taken to
not exceed the maximum junction temperatures; for this
reason this technique should not be used with supplies
exceeding ±10V. For intermediate values of V
CC
,
external resistors between pins 1 and 2 and pins 8 and 9
can be used.
P
(circuit)
= (I
CC
)((+V
CC
) – (V
CC
)) where I
CC
= 16mA at ±15V
P
(xxx)
= [(±V
CC
) – V
out
– (I
col
) (R
col
+ 4)] (I
col
) (%Duty)
For positive V
o
and V
CC
, this is the power in the npn
device. For negative V
o
and V
CC
, this is the power in the
pnp device.
I
col
= V
o
/R
L
or 4mA, whichever is greater. (Include feed-
back R in R
L
.)
R
col
is a resistor (33Ω recommended) between the xxx
collector and ±V
CC
.
The limiting factor for output current and voltage is junction
temperature. Of secondary importance is I
(out)
, which
should not exceed 150mA.
T
j(pnp)
= P
(pnp)
(100 +
θ
ca
) + (P
(cir)
+ P
(npn)
)(θ
ca
) + T
a
,
similar for T
j(npn)
.
T
j(cir)
= P
(cir)
(48 +
θ
ca
) + (P
(pnp)
+ P
(npn)
)(θ
ca
) + T
a
.
REV. 1A January 2004
5
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