Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin TSOP II packages
■
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
14
). If byte high enable (BHE) is LOW, then data from
I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
14
).
Reading from the device is accomplished by taking chip
enable (CE) and output enable (OE) LOW while forcing the
write enable (WE) HIGH. If byte low enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
0
to I/O
7
. If byte high enable (BHE) is LOW,
then data from memory will appear on I/O
8
to I/O
15
. See the
truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil
wide Molded SOJ and 44-pin TSOP II packages.
For a complete list of related documentation,
click here.
■
■
■
■
■
■
Functional Description
The CY7C1020DV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration
[1]
SOJ/TSOP II
Top View
NC
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
4
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
32K x 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
8
A
9
A
10
A
11
A
12
A
13
Notes
1. NC pins are not connected on the die.
A
14
Cypress Semiconductor Corporation
Document Number: 38-05461 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 19, 2014
CY7C1020DV33
Selection Guide
–10 (Industrial)
Maximum access time
Maximum operating current
Maximum CMOS standby current
10
60
3
Unit
ns
mA
mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage temperature ................................ –65
C
to +150
C
Ambient temperature with
power applied ........................................... –55
C
to +125
C
Supply voltage on V
CC
to Relative GND
[2]
...–0.5 V to +4.6 V
DC voltage applied to outputs
in High-Z State
[2]
.................................. –0.5 V to V
CC
+ 0.5 V
DC input voltage
[2]
............................... –0.5 V to V
CC
+ 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage........................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up current ..................................................... > 200 mA
Operating Range
Range
Industrial
Ambient
Temperature
–40 °C to +85 °C
V
CC
3.3 V
0.3 V
Speed
10 ns
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
[2]
Input Load current
Output leakage current
V
CC
operating
supply current
GND < V
I
< V
CC
GND < V
I
< V
CC
, Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
100 MHz
83 MHz
66 MHz
40 MHz
I
SB1
I
SB2
Automatic CE Power-down
Current—TTL Inputs
Automatic CE Power-down
Current—CMOS Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V, or V
IN
< 0.3 V, f = 0
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
0.3
1
1
–10 (Industrial)
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
60
55
45
30
10
3
Max.
Unit
V
V
V
V
A
A
mA
mA
mA
mA
mA
mA
Notes
2. V
IL
(min.) = –2.0 V and V
IH
(max) = V
CC
+ 1 V for pulse durations of less than 5 ns.
Document Number: 38-05461 Rev. *I
Page 2 of 13
CY7C1020DV33
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25C, f = 1 MHz, V
CC
= 3.3 V
Max.
8
8
Unit
pF
pF
Thermal Resistance
[3]
Parameter
JA
JC
Description
Thermal resistance
(Junction to Ambient)
Thermal resistance
(Junction to Case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
SOJ
59.52
36.75
TSOP II
53.91
21.24
Unit
C/W
C/W
AC Test Loads and Waveforms
[4]
Z = 50
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5 V
Rise Time: 1 V/ns
3.0 V
90%
GND
10%
ALL INPUT PULSES
90%
10%
30 pF*
(a)
(b)
Fall Time: 1 V/ns
High-Z characteristics:
R 317
3.3 V
OUTPUT
5 pF
R2
351
(c)
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document Number: 38-05461 Rev. *I
Page 3 of 13
CY7C1020DV33
Switching Characteristics
Over the Operating Range
[5]
Parameter
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU[9]
t
PD[9]
t
DBE
t
LZBE
t
HZBE
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write cycle time
CE LOW to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
WE pulse width
Data set-up to write end
Data hold from write end
WE HIGH to Low-Z
[7]
WE LOW to High-Z
[7, 8]
Byte enable to end of write
7
10
8
8
0
0
7
5
0
3
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
(typical) to the first access
Read cycle time
Address to data valid
Data Hold from Address Change
CE LOW to data valid
OE LOW to data valid
OE LOW to Low-Z
[7]
OE HIGH to High-Z
[7, 8]
CE LOW to Low-Z
[7]
CE HIGH to High-Z
[7, 8]
CE LOW to Power-up
CE HIGH to Power-down
Byte enable to data valid
Byte enable to low-Z
Byte disable to high-Z
0
5
0
10
5
3
5
0
5
3
10
5
100
10
10
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
–10 (Industrial)
Min.
Max.
Unit
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed
7. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. This parameter is guaranteed by design and is not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write and
the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum write cycle time for Write Cycle 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document Number: 38-05461 Rev. *I
Page 4 of 13
CY7C1020DV33
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR [3]
t
R[12]
V
CC
Data retention current
Chip deselect to data retention time
Operation recovery time
V
CC
= V
DR
= 2.0 V, CE > V
CC
– 0.3 V, Industrial
V
IN
> V
CC
– 0.3 V or V
IN
< 0.3 V
0
t
RC
Description
Conditions
Min.
2.0
3
Max.
Unit
V
mA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0 V
t
CDR
CE
V
DR
>
2 V
3.0 V
t
R
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
t
RC
RC
ADDRESS
t
AA
t
OHA
DATA I/O
PREVIOUS DATA VALID
DATA OUT VALID
Read Cycle No. 2 (OE Controlled)
[14, 15]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
BHE, BLE
t
LZOE
t
DBE
t
LZBE
DATA I/O
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZCE
t
HZBE
DATA OUT VALID
t
PD
50%
I
CC
I
SB
t
HZOE
HIGH
IMPEDANCE
Notes:
12. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
s
or stable at V
CC(min.)
> 50
s.
13. Device is continuously selected. OE, CE, BHE and/or BLE = V
IL
.
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE transition LOW.
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