Data Sheet, Rev. 3
June 2001
FW804 PHY
IEEE
* 1394A
Four-Cable Transceiver/Arbiter Device
Distinguishing Features
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Supports LPS/link-on as a part of PHY-link inter-
face.
Supports provisions of
IEEE
1394-1995
Standard
for a High Performance Serial Bus.
Fully interoperable with
FireWire
†
implementation
of
IEEE
1394-1995.
Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
Separate cable bias and driver termination voltage
supply for each port.
Compliant with
IEEE
P1394a Draft 2.0
Standard
for a High Performance Serial Bus
(Supple-
ment)
Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
While unpowered and connected to the bus, will not
drive TPBIAS on a connected port even if receiving
incoming bias voltage on that port.
Does not require external filter capacitors for PLL.
Does not require a separate 5 V supply for 5 V link
controller interoperability.
Interoperable across 1394 cable with 1394 physical
layers (PHY) using 5 V supplies.
Interoperable with 1394 link-layer controllers using
5 V supplies.
Powerdown features to conserve energy in battery-
powered applications include:
— Device powerdown pin.
— Link interface disable using LPS.
— Inactive ports power down.
Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
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Other Features
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80-pin TQFP package.
Single 3.3 V supply operation.
Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
25 MHz crystal oscillator and PLL provide transmit/
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s, and link-layer controller clock at
50 MHz.
Node power-class information signaling for system
power management.
Multiple separate package signals provided for
analog and digital supplies and grounds.
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Features
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Provides four fully compliant cable ports at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
Fully supports open HCI requirements.
Supports arbitrated short bus reset to improve
utilization of the bus.
Supports ack-accelerated arbitration and fly-by
concatenation.
Supports connection debounce.
Supports multispeed packet concatenation.
Supports PHY pinging and remote PHY access
packets.
Fully supports suspend/resume.
Supports PHY-link interface initialization and reset.
Supports 1394a-2000 register set.
Description
The Agere Systems Inc. FW804 device provides the
analog physical layer functions needed to implement
a four-port node in a cable-based
IEEE
1394-1995
and
IEEE
1394a-2000 network.
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*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
†
FireWire
is a registered trademark of Apple Computer, Inc.
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FW804 PHY
IEEE
1394A
Four-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 3
June 2001
Table of Contents
Contents
Page
Distinguishing Features ............................................................................................................................................ 1
Features ................................................................................................................................................................... 1
Other Features ......................................................................................................................................................... 1
Description................................................................................................................................................................ 1
Signal Information..................................................................................................................................................... 6
Application Information ........................................................................................................................................... 10
Crystal Selection Considerations............................................................................................................................ 11
1394 Application Support Contact Information ....................................................................................................... 12
Absolute Maximum Ratings.................................................................................................................................... 12
Electrical Characteristics ........................................................................................................................................ 13
Timing Characteristics ............................................................................................................................................ 16
Timing Waveforms.................................................................................................................................................. 17
Internal Register Configuration............................................................................................................................... 18
Outline Diagrams.................................................................................................................................................... 23
Ordering Information............................................................................................................................................... 23
List of Figures
Figures
Page
Figure 1. Block Diagram ........................................................................................................................................... 5
Figure 2. Pin Assignments........................................................................................................................................ 6
Figure 3. Typical External Component Connections .............................................................................................. 10
Figure 4. Typical Port Termination Network ........................................................................................................... 11
Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ............................................................. 17
Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms....................................................................... 17
List of Tables
Tables
Page
Table 1. Signal Descriptions..................................................................................................................................... 7
Table 2. Absolute Maximum Ratings...................................................................................................................... 12
Table 3. Analog Characteristics.............................................................................................................................. 13
Table 4. Driver Characteristics ............................................................................................................................... 14
Table 5. Device Characteristics.............................................................................................................................. 15
Table 6. Switching Characteristics ......................................................................................................................... 16
Table 7. Clock Characteristics ............................................................................................................................... 16
Table 8. PHY Register Map for the Cable Environment ........................................................................................ 18
Table 9. PHY Register Fields for the Cable Environment ...................................................................................... 18
Table 10. PHY Register Page 0: Port Status Page ............................................................................................... 20
Table 11. PHY Register Port Status Page Fields .................................................................................................. 21
Table 12. PHY Register Page 1: Vendor Identification Page ............................................................................... 22
Table 13. PHY Register Vendor Identification Page Fields .................................................................................... 22
2
Agere Systems Inc.
Data Sheet, Rev. 3
June 2001
FW804 PHY
IEEE
1394A
Four-Cable Transceiver/Arbiter Device
Both the TPA and TPB cable interfaces incorporate
differential comparators to monitor the line states
during initialization and arbitration. The outputs of
these comparators are used by the internal logic to
determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage.
The value of this common-mode voltage is used during
arbitration to set the speed of the next packet
transmission. In addition, the TPB channel monitors
the incoming cable common-mode voltage for the
presence of the remotely supplied twisted-pair bias
voltage. This monitor is called bias-detect.
The TPBIAS circuit monitors the value of incoming
TPA pair common-mode voltage when local TPBIAS is
inactive. Because this circuit has an internal current
source and the connected node has a current sink, the
monitored value indicates the cable connection status.
This monitor is called connect-detect.
Both the TPB bias-detect monitor and TPBIAS
connect-detect monitor are used in suspend/resume
signaling and cable connection detection.
The PHY provides a 1.86 V nominal bias voltage for
driver load termination. This bias voltage, when seen
through a cable by a remote receiver, indicates the
presence of an active connection. The value of this
bias voltage has been chosen to allow interoperability
between transceiver chips operating from 5 V or 3 V
nominal supplies. This bias voltage source should be
stabilized by using an external filter capacitor of
approximately 0.33
µF.
The transmitter circuitry, the receiver circuitry, and the
twisted-pair bias voltage circuity are all disabled with a
powerdown condition. The powerdown condition
occurs when the PD input is high. The port transmitter
circuitry, the receiver circuitry, and the TPBIAS output
are also disabled when the port is disabled,
suspended, or disconnected.
The line drivers in the PHY operate in a high-
impedance current mode and are designed to work
with external 112
Ω
line-termination resistor networks.
One network is provided at each end of each twisted-
pair cable. Each network is composed of a pair of
series-connected 56
Ω
resistors. The midpoint of the
pair of resistors that is directly connected to the
twisted-pair A (TPA) signals is connected to the
TPBIAS voltage signal. The midpoint of the pair of
resistors that is directly connected to the twisted-pair B
(TPB) signals is coupled to ground through a parallel
RC network with recommended resistor and capacitor
values of 5 kΩ and 220 pF, respectively.
Description
(continued)
Each cable port incorporates two differential line
transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining
connection status, for initialization and arbitration, and
for packet reception and transmission. The PHY is
designed to interface with a link-layer controller (LLC).
The PHY requires either an external 24.576 MHz
crystal or crystal oscillator. The internal oscillator
drives an internal phase-locked loop (PLL), which
generates the required 400 MHz reference signal. The
400 MHz reference signal is internally divided to
provide the 49.152 MHz, 98.304 MHz, and
196.608 MHz clock signals that control transmission of
the outbound encoded strobe and data information.
The 49.152 MHz clock signal is also supplied to the
associated LLC for synchronization of the two chips
and is used for resynchronization of the received data.
The powerdown function, when enabled by the PD
signal high, stops operation of the PLL and disables all
circuitry except the cable-not-active signal circuitry.
The PHY supports an isolation barrier between itself
and its LLC. When /ISO is tied high, the link interface
outputs behave normally. When /ISO is tied low,
internal differentiating logic is enabled, and the outputs
become short pulses, which can be coupled through a
capacitor or transformer as described in the
IEEE
1394-1995 Annex J. To operate with bus-keeper
isolation, the /ISO pin of the FW804 must be tied high.
Data bits to be transmitted through the cable ports are
received from the LLC on two, four, or eight data lines
(D[0:7]), and are latched internally in the PHY in
synchronization with the 49.152 MHz system clock.
These bits are combined serially, encoded, and
transmitted at 98.304 Mbits/s, 196.608 Mbits/s, or
393.216 Mbits/s as the outbound data-strobe
information stream. During transmission, the encoded
data information is transmitted differentially on the TPA
and TPB cable pair(s).
During packet reception, the TPA and TPB
transmitters of the receiving cable port are disabled,
and the receivers for that port are enabled. The
encoded data information is received on the TPA and
TPB cable pair. The received data-strobe information
is decoded to recover the receive clock signal and the
serial data bits. The serial data bits are split into two,
four, or eight parallel streams, resynchronized to the
local system clock, and sent to the associated LLC.
The received data is also transmitted (repeated) out of
the other active (connected) cable ports.
Agere Systems Inc.
3
FW804 PHY
IEEE
1394A
Four-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 3
June 2001
When the power supply of the PHY is removed while
the twisted-pair cables are connected, the PHY
transmitter and receiver circuitry has been designed to
present a high impedance to the cable in order to not
load the TPBIAS signal voltage on the other end of the
cable.
For reliable operation, the TPBn signals must be
terminated using the normal termination network
regardless of whether a cable is connected to a port or
not connected to a port. For those applications, when
FW804 is used with one or more of the ports not
brought out to a connector, those unused ports may be
left unconnected without normal termination. When a
port does not have a cable connected, internal
connect-detect circuitry will keep the port in a
disconnected state.
Note:
All gap counts on all nodes of a 1394 bus must
be identical. This may be accomplished by using
PHY configuration packets (see Section 4.3.4.3
of
IEEE
1394-1995 standard) or by using two
bus resets, which resets the gap counts to the
maximum level (3Fh).
The link power status (LPS) signal works with the
C/LKON signal to manage the LLC power usage of the
node. The LPS signal indicates that the LLC of the
node is powered up or powered down. If LPS is
inactive for more than 1.2
µs
and less than 25
µs,
PHY/link interface is reset. If LPS is inactive for greater
than 25
µs,
the PHY will disable the PHY/link interface
to save power. FW804 continues its repeater function.
If the PHY then receives a link-on packet, the C/LKON
signal is activated to output a 6.114 MHz signal, which
can be used by the LLC to power itself up. Once the
LLC is powered up, the LPS signal communicates this
to the PHY and the PHY/link interface is enabled.
C/LKON signal is turned off when LPS is active or
when a bus reset occurs, provided the interrupt that
caused C/LKON is not present.
Two of the signals are used to set up various test
conditions used in manufacturing. These signals, SE
and SM, should be connected to V
SS
for normal
operation.
Description
(continued)
The value of the external resistors are specified to
meet the standard specifications when connected in
parallel with the internal receiver circuits.
The driver output current, along with other internal
operating currents, is set by an external resistor. This
resistor is connected between the R0 and R1 signals
and has a value of 2.49 kΩ
±
1%.
The FW804 supports suspend/resume as defined in
the
IEEE
1394a-2000 specification. The suspend
mechanism allows an FW804 port to be put into a
suspended state. In this state, a port is unable to
transmit or receive data packets, however, it remains
capable of detecting connection status changes and
detecting incoming TPBias. When all ports of the
FW804 are suspended, all circuits except the bias
voltage reference generator, and bias detection
circuits are powered down, resulting in significant
power savings. The use of suspend/resume is
recommended.
Four signals are used as inputs to set four
configuration status bits in the self-identification (self-
ID) packet. These signals are hardwired high or low as
a function of the equipment design. PC[0:2] are the
three signals that indicate either the need for power
from the cable or the ability to supply power to the
cable. The fourth signal, C/LKON, as an input,
indicates whether a node is a contender for bus
manager. When the C/LKON signal is asserted, it
means the node is a contender for bus manager.
When the signal is not asserted, it means that the
node is not a contender. The C bit corresponds to bit
20 in the self-ID packet, PC0 corresponds to bit 21,
PC1 corresponds to bit 22, and PC2 corresponds to bit
23 (see Table 4-29 of the
IEEE
1394-1995 standard
for additional details).
A powerdown signal (PD) is provided to allow a
powerdown mode where most of the PHY circuits are
powered down to conserve energy in battery-powered
applications. The internal logic in FW804 is reset as
long as the powerdown signal is asserted. A cable
status signal, CNA, provides a high output when none
of the twisted-pair cable ports are receiving incoming
bias voltage. This output is not debounced. The CNA
output can be used to determine when to power the
PHY down or up. In the powerdown mode, all circuitry
is disabled except the CNA circuitry. It should be noted
that when the device is powered down, it does not act
in a repeater mode.
4
Agere Systems Inc.
Data Sheet, Rev. 3
June 2001
FW804 PHY
IEEE
1394A
Four-Cable Transceiver/Arbiter Device
Description
(continued)
CPS
LPS
/ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PC0
PC1
PC2
C/LKON
SE
SM
LINK
INTERFACE
I/O
TPA0+
TPA0–
ARBITRATION
AND
CONTROL
STATE
MACHINE
LOGIC
RECEIVED
DATA
DECODER/
RETIMER
BIAS
VOLTAGE
AND
CURRENT
GENERATOR
R0
R1
TPBIAS0
CABLE PORT 0
TPB0+
TPB0–
PD
TPA1+
TPA1–
TRANSMIT
DATA
ENCODER
CABLE PORT 1
TPBIAS1
TPB1+
TPB1–
TPA2+
TPA2–
CABLE PORT 2
TPBIAS2
TPB2+
TPB2–
TPA3+
TPA3–
CABLE PORT 3
TPBIAS3
TPB3+
TPB3–
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND
CLOCK
GENERATOR
/RESET
XI
XO
5-5459.g (F)
Figure 1. Block Diagram
Agere Systems Inc.
5
Microchip MCU
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