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FW323: 产品描述1394A PCI PHY/Link Open Host Controller Interface; 文件大小533KB，共152页; 制造商Agere System(LSI Logic)

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1394A PCI PHY/Link Open Host Controller Interface

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Data Sheet, Rev. 2

October 2001

FW323 05

1394A PCI PHY/Link Open Host Controller Interface

Features

1394a-2000 OHCI link and PHY core function in sin-

gle device:

— Enables smaller, simpler, more efficient mother-

board and add-in card designs by replacing two

components with one

— Enables lower system costs

— Leverages proven 1394a-2000 PHY core design

— Demonstrated compatibility with current

Microsoft

Windows

drivers and common applications

— Demonstrated interoperability with existing, as well

as older, 1394 consumer electronics and periph-

erals products

— Feature-rich implementation for high performance

in common applications

— Supports low-power system designs (CMOS

implementation, power management features)

— Provides LPS, LKON, and CNA outputs to support

legacy power management implementations

OHCI:

— Complies with OHCI 1.1 WHQL requirements

— Complies with

Microsoft Windows

Logo Program

System and Device Requirements

— Listed on

Windows

Hardware Compatibility List

http://www.microsoft.com/hcl/results.asp

— Compatible with

Microsoft Windows

and

MacOS

operating systems

— 4 Kbyte isochronous transmit FIFO

— 2 Kbyte asynchronous transmit FIFO

— 4 Kbyte isochronous receive FIFO

— 2 Kbyte asychronous receive FIFO

— Dedicated asynchronous and isochronous

descriptor-based DMA engines

— Eight isochronous transmit contexts

— Eight isochronous receive contexts

— Prefetches isochronous transmit data

— Supports posted write transactions

1394a-2000 PHY core:

— Compliant with

IEEE

1394a-2000,

Standard for a

High Performance Serial Bus

(Supplement)

— Provides three fully compliant cable ports, each

supporting 400 Mbits/s, 200 Mbits/s, and

100 Mbits/s traffic

— Supports extended BIAS_HANDSHAKE time for

enhanced interoperability with camcorders

— While unpowered and connected to the bus, will

not drive TPBIAS on a connected port even if

receiving incoming bias voltage on that port

— Does not require external filter capacitor for PLL

— Supports PHY core-link interface initialization and

reset

— Supports link-on as a part of the internal

PHY core-link interface

— 25 MHz crystal oscillator and internal PLL provide

transmit/receive data at 100 Mbits/s, 200 Mbits/s,

and 400 Mbits/s, and internal link-layer controller

clock at 50 MHz

— Interoperable across 1394 cable with 1394 phys-

ical layers (PHY core) using 5 V supplies

— Node power-class information signaling for

system power management

— Supports ack-accelerated arbitration and fly-by

concatenation

— Supports arbitrated short bus reset to improve

utilization of the bus

— Fully supports suspend/resume

— Supports connection debounce

— Supports multispeed packet concatenation

— Supports PHY pinging and remote PHY access

packets

— Reports cable power fail interrupt when voltage at

CPS pin falls below 7.5 V

— Separate cable bias and driver termination voltage

supply for each port

Link:

— Cycle master and isochronous resource manager

capable

— Supports 1394a-2000 acceleration features

FW323 05

1394A PCI PHY/Link Open Host Controller Interface

Data Sheet, Rev. 2

October 2001

Table of Contents

Contents

Page

Features ...................................................................................................................................................................1

FW323 Functional Overview ....................................................................................................................................7

Other Features ......................................................................................................................................................... 7

FW323 Functional Description ........................................................................................................................... 7

PCI Core ............................................................................................................................................................7

Isochronous Data Transfer ................................................................................................................................ 8

Asynchronous Data Transfer .............................................................................................................................8

Asynchronous Register ...................................................................................................................................... 8

Serial EEPROM Interface ..................................................................................................................................9

Link Core ............................................................................................................................................................9

PHY Core ........................................................................................................................................................... 9

Pin Information ....................................................................................................................................................... 13

Application Schematic ............................................................................................................................................ 18

Internal Registers ...................................................................................................................................................20

PCI Configuration Registers ............................................................................................................................ 20

Vendor ID Register .......................................................................................................................................... 21

Device ID Register ........................................................................................................................................... 22

PCI Command Register ................................................................................................................................... 23

PCI Status Register ......................................................................................................................................... 25

Class Code and Revision ID Register .............................................................................................................. 26

Latency Timer and Class Cache Line Size Register ........................................................................................ 27

Header Type and BIST Register ......................................................................................................................28

OHCI Base Address Register .......................................................................................................................... 30

PCI Subsystem Identification Register ............................................................................................................. 32

PCI Power Management Capabilities Pointer Register .................................................................................... 32

Interrupt Line and Pin Register ........................................................................................................................ 33

MIN_GNT and MAX_LAT Register .................................................................................................................. 34

PCI OHCI Control Register .............................................................................................................................. 35

Capability ID and Next Item Pointer Register .................................................................................................. 37

Power Management Capabilities Register ....................................................................................................... 38

Power Management Control and Status Register ............................................................................................40

Power Management Extension Register .......................................................................................................... 42

OHCI Registers ................................................................................................................................................ 43

OHCI Version Register .................................................................................................................................... 46

GUID ROM Register ........................................................................................................................................ 48

Asynchronous Transmit Retries Register ......................................................................................................... 50

CSR Data Register .......................................................................................................................................... 52

CSR Compare Register ................................................................................................................................... 54

CSR Control Register ...................................................................................................................................... 56

Configuration ROM Header Register ...............................................................................................................58

Bus Identification Register ............................................................................................................................... 60

Bus Options Register .......................................................................................................................................62

GUID High Register ......................................................................................................................................... 64

GUID Low Register .......................................................................................................................................... 66

Configuration ROM Mapping Register ............................................................................................................. 68

Posted Write Address Low Register ................................................................................................................ 70

Posted Write Address High Register ...............................................................................................................72

Vendor ID Register .......................................................................................................................................... 74

Host Controller Control Register ......................................................................................................................76

Self-ID Count Register ..................................................................................................................................... 80

Isochronous Receive Channel Mask High Register ......................................................................................... 82

Agere Systems Inc.

Data Sheet, Rev. 2

October 2001

FW323 05

1394A PCI PHY/Link Open Host Controller Interface

Table of Contents

(continued)

Contents

Page

Isochronous Receive Channel Mask Low Register .......................................................................................... 84

Interrupt Event Register ................................................................................................................................... 86

Interrupt Mask Register .................................................................................................................................... 89

Isochronous Transmit Interrupt Event Register ................................................................................................ 91

Isochronous Transmit Interrupt Mask Register ................................................................................................ 93

Isochronous Receive Interrupt Event Register ................................................................................................. 94

Isochronous Receive Interrupt Mask Register ................................................................................................. 96

Fairness Control Register ................................................................................................................................ 97

Link Control Register ........................................................................................................................................99

Node Identification Register ........................................................................................................................... 101

PHY Core Layer Control Register .................................................................................................................. 103

Isochronous Cycle Timer Register ................................................................................................................. 105

Asynchronous Request Filter High Register .................................................................................................. 107

Asynchronous Request Filter Low Register ................................................................................................... 110

Physical Request Filter High Register ............................................................................................................113

Physical Request Filter Low Register ............................................................................................................116

Asynchronous Context Control Register ........................................................................................................ 119

Asynchronous Context Command Pointer Register ....................................................................................... 121

Isochronous Transmit Context Control Register ............................................................................................ 123

Isochronous Transmit Context Command Pointer Register ........................................................................... 125

Isochronous Receive Context Control Register ............................................................................................. 127

Isochronous Receive Context Command Pointer Register ............................................................................ 129

Isochronous Receive Context Match Register ............................................................................................... 131

FW323 Vendor Specific Registers ................................................................................................................. 133

Isochronous DMA Control .............................................................................................................................. 134

Asynchronous DMA Control ........................................................................................................................... 135

Link Options ................................................................................................................................................... 136

Crystal Selection Considerations ..........................................................................................................................138

Load Capacitance .......................................................................................................................................... 138

Board Layout ..................................................................................................................................................138

Absolute Maximum Ratings .................................................................................................................................. 138

Electrical Characteristics ......................................................................................................................................139

Timing Characteristics .......................................................................................................................................... 141

ac Characteristics of Serial EEPROM Interface Signals ...................................................................................... 141

Internal Register Configuration ............................................................................................................................. 144

PHY Core Register Map for Cable Environment ............................................................................................ 144

PHY Core Register Fields for Cable Environment .........................................................................................145

Outline Diagrams ..................................................................................................................................................150

128-Pin TQFP ................................................................................................................................................ 150

Figure

Page

Figure 1. FW323 Functional Block Diagram .............................................................................................................7

Figure 2. PHY Core Block Diagram ........................................................................................................................ 12

Figure 3. Pin Assignments for FW323 .................................................................................................................... 13

Figure 4. Application Schematic for FW323 ........................................................................................................... 19

Figure 5. Bus Timing ............................................................................................................................................ 142

Figure 6. Write Cycle Timing ................................................................................................................................ 142

Figure 7. Data Validity .......................................................................................................................................... 142

Figure 8. Start and Stop Definition ....................................................................................................................... 143

Figure 9. Output Acknowledge ............................................................................................................................. 143

Agere Systems Inc.

FW323 05

1394A PCI PHY/Link Open Host Controller Interface

Data Sheet, Rev. 2

October 2001

Table of Contents

(continued)

Table

Page

Table 1. Pin Descriptions ........................................................................................................................................14

Table 2. Bit-Field Access Tag Description ..............................................................................................................20

Table 3. PCI Configuration Register Map ...............................................................................................................20

Table 4. Vendor ID Register ...................................................................................................................................21

Table 5. Device ID Register ....................................................................................................................................22

Table 6. PCI Command Register ............................................................................................................................23

Table 7. PCI Command Register Description .........................................................................................................24

Table 8. PCI Status Register ..................................................................................................................................25

Table 9. Class Code and Revision ID Register .....................................................................................................26

Table 10. Class Code and Revision ID Register Description .................................................................................27

Table 11. Latency Timer and Class Cache Line Size Register ..............................................................................27

Table 12. Latency Timer and Class Cache Line Size Register Description ..........................................................28

Table 13. Header Type and BIST Register ............................................................................................................28

Table 14. Header Type and BIST Register Description .........................................................................................29

Table 15. OHCI Base Address Register .................................................................................................................30

Table 16. OHCI Base Address Register Description ..............................................................................................31

Table 17. PCI Subsystem Identification Register Description ................................................................................32

Table 18. PCI Power Management Capabilities Pointer Register ..........................................................................32

Table 19. Interrupt Line and Pin Register ...............................................................................................................33

Table 20. Interrupt Line and Pin Register Description ............................................................................................33

Table 21. MIN_GNT and MAX_LAT Register .........................................................................................................34

Table 22. MIN_GNT and MAX_LAT Register Description ......................................................................................34

Table 23. PCI OHCI Control Register ....................................................................................................................35

Table 24. PCI OHCI Control Register Description ..................................................................................................36

Table 25. Capability ID and Next Item Pointer Register .........................................................................................37

Table 26. Capability ID and Next Item Pointer Register Description ......................................................................37

Table 27. Power Management Capabilities Register .............................................................................................38

Table 28. Power Management Capabilities Register Description ..........................................................................39

Table 29. Power Management Control and Status Register .................................................................................40

Table 30. Power Management Control and Status Register Description ...............................................................41

Table 31. Power Management Extension Register ................................................................................................42

Table 32. Power Management Extension Register Description ............................................................................42

Table 33. OHCI Register Map ................................................................................................................................43

Table 34. OHCI Version Register ...........................................................................................................................46

Table 35. OHCI Version Register Description ........................................................................................................47

Table 36. GUID ROM Register ..............................................................................................................................48

Table 37. GUID ROM Register Description ............................................................................................................49

Table 38. Asynchronous Transmit Retries Register ..............................................................................................50

Table 39. Asynchronous Transmit Retries Register Description ............................................................................51

Table 40. CSR Data Register .................................................................................................................................52

Table 41. CSR Data Register Description ..............................................................................................................53

Table 42. CSR Compare Register ..........................................................................................................................54

Table 43. CSR Compare Register Description .......................................................................................................55

Table 44. CSR Control Register .............................................................................................................................56

Table 45. CSR Control Register Description .........................................................................................................57

Table 46. Configuration ROM Header Register ......................................................................................................58

Table 47. Configuration ROM Header Register Description ..................................................................................59

Table 48. Bus Identification Register ......................................................................................................................60

Table 49. Bus Identification Register Description ...................................................................................................61

Table 50. Bus Options Register ..............................................................................................................................62

Table 51. Bus Options Register Description ...........................................................................................................63

Agere Systems Inc.

Data Sheet, Rev. 2

October 2001

FW323 05

1394A PCI PHY/Link Open Host Controller Interface

Table of Contents

(continued)

Table

Page

Table 52. GUID High Register ................................................................................................................................64

Table 53. GUID High Register Description .............................................................................................................65

Table 54. GUID Low Register .................................................................................................................................66

Table 55. GUID Low Register Description ..............................................................................................................67

Table 56. Configuration ROM Mapping Register ....................................................................................................68

Table 57. Configuration ROM Mapping Register Description .................................................................................69

Table 58. Posted Write Address Low Register .......................................................................................................70

Table 59. Posted Write Address Low Register Description ....................................................................................71

Table 60. Posted Write Address High Register ......................................................................................................72

Table 61. Posted Write Address High Register Description ...................................................................................73

Table 62. Vendor ID Register .................................................................................................................................74

Table 63. Vendor ID Register Description ..............................................................................................................75

Table 64. Host Controller Control Register .............................................................................................................76

Table 65. Host Controller Control Register Description ..........................................................................................77

Table 66. Self-ID Buffer Pointer Register ...............................................................................................................78

Table 67. Self-ID Buffer Pointer Register Description ............................................................................................79

Table 68. Self-ID Count Register ............................................................................................................................80

Table 69. Self-ID Count Register Description .........................................................................................................81

Table 70. Isochronous Receive Channel Mask High Register ...............................................................................82

Table 71. Isochronous Receive Channel Mask High Register Description ............................................................83

Table 72. Isochronous Receive Channel Mask Low Register ................................................................................84

Table 73. Isochronous Receive Channel Mask Low Register Description ............................................................85

Table 74. Interrupt Event Register ..........................................................................................................................86

Table 75. Interrupt Event Register Description .......................................................................................................87

Table 76. Interrupt Mask Register ..........................................................................................................................89

Table 77. Interrupt Mask Register Description .......................................................................................................90

Table 78. Isochronous Transmit Interrupt Event Register ......................................................................................91

Table 79. Isochronous Transmit Interrupt Event Register Description ...................................................................92

Table 80. Isochronous Transmit Interrupt Mask Register .......................................................................................93

Table 81. Isochronous Receive Interrupt Event Register .......................................................................................94

Table 82. Isochronous Receive Interrupt Event Description ..................................................................................95

Table 83. Isochronous Receive Interrupt Mask Register ........................................................................................96

Table 84. Fairness Control Register .......................................................................................................................97

Table 85. Fairness Control Register Description ....................................................................................................98

Table 86. Link Control Register .............................................................................................................................99

Table 87. Link Control Register Description ........................................................................................................100

Table 88. Node Identification Register .................................................................................................................101

Table 89. Node Identification Register Description ..............................................................................................102

Table 90. PHY Core Layer Control Register ........................................................................................................103

Table 91. PHY Core Layer Control Register Description .....................................................................................104

Table 92. Isochronous Cycle Timer Register .......................................................................................................105

Table 93. Isochronous Cycle Timer Register Description ....................................................................................106

Table 94. Asychronous Request Filter High Register ..........................................................................................107

Table 95. Asynchronous Request Filter High Register Description ......................................................................108

Table 96. Asynchronous Request Filter Low Register ........................................................................................110

Table 97. Asynchronous Request Filter Low Register Description ......................................................................111

Table 98. Physical Request Filter High Register ..................................................................................................113

Table 99. Physical Request Filter High Register Description ...............................................................................114

Table 100. Physical Request Filter Low Register ................................................................................................116

Table 101. Physical Request Filter Low Register Description ..............................................................................117

Table 102. Asynchronous Context Control Register ............................................................................................119

Agere Systems Inc.

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