HIGH-SPEED 3.3V
4K x 16 DUAL-PORT
STATIC RAM
Features
x
x
x
IDT70V24S/L
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
Low-power operation
– IDT70V24S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V24L
Active: 380mW (typ.)
Standby: 660
µ
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
x
x
x
x
x
x
x
x
IDT70V24 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
(1,2)
BUSY
R
(1,2)
Address
Decoder
12
L
A
11L
A
0L
MEMORY
ARRAY
12
Address
Decoder
A
11R
A
0R
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
INT
R
(2)
2911 drw 01
M/
S
MARCH 2000
1
DSC-2911/8
©2000 Integrated Device Technology, Inc.
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V24 is a high-speed 4K x 16 Dual-Port Static RAM. The
IDT70V24 is designed to be used as a stand-alone 64K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 32-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asyn-chronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 400mW of power.
The IDT70V24 is packaged in a ceramic 84-pin PGA, an 84-Pin
PLCC and a 100-pin Thin Quad Flatpack.
V
CC
R/
W
L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
SEM
L
CE
L
UB
L
LB
L
Pin Configurations
(1,2,3)
OE
L
INDEX
11 10 9 8 7 6 5 4
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
3 2 1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
N/C
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
IDT70V24J
J84-1
(4)
84-Pin PLCC
Top View
(5)
INT
L
BUSY
L
GND
M/
S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
2911 drw 02
58
57
29
56
30
55
31
32
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
N/C
A
11R
A
10R
A
9R
A
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
SEM
R
CE
R
UB
R
LB
R
OE
R
R/
W
R
GND
A
7R
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
SEM
L
CE
L
UB
L
LB
L
V
CC
R/
W
L
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
73
72
71
70
69
68
67
66
N/C
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
65
64
63
62
61
60
59
58
57
56
55
54
53
52
IDT70V24PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
OE
L
Index
INT
L
BUSY
L
GND
M/
S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
2911 drw 03
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
6.42
2
SEM
R
CE
R
UB
R
LB
R
R/
W
R
GND
N/C
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
OE
R
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
63
61
60
58
55
54
51
48
46
45
42
11
I/O
7L
66
I/O
5L
64
I/O
4L
62
I/O
2L
59
I/O
0L
56
OE
L
49
SEM
L
50
LB
L
47
A
11L
44
A
10L
43
A
7L
40
10
I/O
10L
67
I/O
8L
65
I/O
6L
I/O
3L
I/O
1L
57
UB
L
53
CE
L
52
N/C
A
9L
A
8L
41
A
5L
39
09
I/O
11L
69
I/O
9L
68
GND
V
CC
R/W
L
A
6L
38
A
4L
37
08
I/O
13L
72
I/O
12L
71
73
33
A
3L
35
A
2L
34
07
I/O
15L
75
I/O
14L
70
V
CC
74
BUSY
L
IDT70V24G
G84-3
(4)
84-Pin PGA
Top View
(5)
32
A
0L
31
INT
L
36
06
I/O
0R
76
GND
77
GND
78
GND
28
M/S
29
A
1L
30
05
I/O
1R
79
I/O
2R
80
V
CC
A
0R
INT
R
26
BUSY
R
27
04
I/O
3R
81
I/O
4R
83
7
11
12
A
2R
23
A
1R
25
03
I/O
5R
82
1
I/O
7R
2
5
GND
8
GND
10
SEM
R
14
17
20
A
5R
22
A
3R
24
02
I/O
6R
84
3
I/O
9R
I/O
10R
4
I/O
13R
6
I/O
15R
9
R/W
R
15
UB
R
13
A
11R
16
A
8R
18
A
6R
19
A
4R
21
01
I/O
8R
A
I/O
11R
B
I/O
12R
C
I/O
14R
D
OE
R
E
LB
R
F
CE
R
G
N/C
H
A
10R
J
A
9R
K
A
7R
L
2911 drw 04
Index
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2911 tbl 01
CE
L
R/
W
L
CE
R
R/
W
R
OE
L
A
0L
- A
11L
I/O
0L
- I/O
15L
OE
R
A
0R
- A
11R
I/O
0R
- I/O
15R
SEM
L
UB
L
LB
L
INT
L
BUSY
L
SEM
R
UB
R
LB
R
INT
R
BUSY
R
M/
S
V
CC
GND
6.42
3
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
Outputs
CE
H
X
L
L
L
L
L
L
X
R/
W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Mode
Deselected: Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
2911 tbl 02
NOTE:
1. A
0L
— A
11L
≠
A
0R
— A
11R
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
Outputs
CE
H
X
H
X
L
L
R/
W
H
H
↑
↑
X
X
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
I/O
8-15
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
I/O
0-7
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write D
IN0
into Semaphore Flag
Write D
IN0
into Semaphore Flag
Not Allowed
Not Allowed
2911 tbl 03
____
____
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all of the I/O's (I/O
0
-I/O
15
). These eight semaphores are addressed by A
0
-A
2
.
6.42
4
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +4.6
Unit
V
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Commercial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
3.3V
+
0.3V
3.3V
+
0.3V
2911 tbl 05
T
BIAS
T
STG
I
OUT
-55 to +125
-55 to +125
50
o
C
C
Industrial
o
NOTES:
1. This is the parameter T
A
.
mA
2911 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period over V
TERM
> Vcc + 0.3V
.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
CC
+0.3
(2)
0.8
Unit
V
V
V
V
2911 tbl 06
(TA = +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
11
Unit
pF
pF
2911 tbl 07
Capacitance
V
IL
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.3V.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V ± 0.3V)
70V24S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.6V, V
IN
= 0V to V
CC
Min.
___
70V24L
Min.
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2911 tbl 08
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
___
___
___
___
2.4
2.4
NOTE:
1. At V
CC
< 2.0V input leakages are undefined.
6.42
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
