AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
DRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• MIL-STD 883
• SMD Planned
1 MEG x 16 DRAM
3.3V, EDO PAGE MODE,
OPTIONAL EXTENDED REFRESH
PIN ASSIGNMENT (Top View)
44/50-Pin SOJ/LCC/Gull Wing
450mil
FEATURES
• JEDEC- and industry-standard x16 timing, functions,
pinouts and packages
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V
power supply
• All device pins are TTL-compatible
• Refresh modes:
?
R
?
A
/
S ONLY,
?
C
?
A
/
S-BEFORE-?R
?
A
/
S (CBR),
HIDDEN
• BYTE WRITE access cycles
• 1,024-cycle refresh (10 row-, 10 column-addresses)
• Low power, 0.3mW standby; 180mW active, typical
• Extended Data-Out (EDO) PAGE access cycle
• 5V-tolerant I/Os (5.5V maximum V
IH
level)
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
Vss
DQ16
DQ15
DQ14
DQ13
Vss
DQ12
DQ11
DQ10
DQ9
NC
OPTIONS
• Timing
60ns access (Contact Factory)
70ns access
80ns access
• Refresh Rate
Standard 16ms period
• Packages
Ceramic SOJ
Ceramic Gull Wing
Ceramic LCC
MARKING
-6
-7
-8
None
ECJ No. 506
ECG No. 604
EC No. 213
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
Vcc
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL
CASH
OE
A9
A8
A7
A6
A5
A4
Vss
KEY TIMING PARAMETERS
SPEED
-6
-7
-8
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
105ns
125ns
150ns
60ns
70ns
80ns
25ns
30ns
40ns
30ns
35ns
40ns
15ns
20ns
20ns
12ns
12ns
20ns
GENERAL DESCRIPTION
The AS4LC1M16 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x16 con-
figuration. The AS4LC1M16 has both BYTE WRITE and
WORD WRITE access cycles via two
?
C
?
A
/
S pins (?C
?
A
?
S
/
L and
?
C
?
A
?
S
?
H). These function in a similar manner to a single
?
C
?
AS
of other DRAMs in that either
?
C
?
AS
/
L or C
?
A
?
S
?
H will generate
?
?
AS4LC1M16
REV. 3/97
DS000020
an internal
?
C
?
A
/
S.
The AS4LC1M16
?
C
?
A
/
S function and timing are deter-
mined by the first
?
C
?
A
/
S (?C
?
A
?
S
/
L or
?
C
?
A
?
S
?
H) to transition LOW
and the last
?
C
?
A
/
S to transition back HIGH. Use of only one
of the two results in a BYTE WRITE cycle.
?
CASL transitioning
? ? /
LOW selects an access cycle for the lower byte (DQ1-DQ8)
and
?
C
?
A
?
S
?
H transitioning LOW selects an access cycle for the
upper byte (DQ9-DQ16).
Each bit is uniquely addressed through the 20 address bits
during READ or WRITE cycles. These are entered 10 bits
(A0 -A9) at a time.
?
R
?
A
/
S is used to latch the first 10 bits and
?
C
?
A
/
S the latter 10 bits. The
?
C
?
A
/
S function also determines
whether the cycle will be a refresh cycle (?R
?
A
/
S ONLY) or an
active cycle (READ, WRITE or READ WRITE) once
?
R
?
A
/
S
goes LOW.
2-93
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
GENERAL DESCRIPTION (continued)
The
?
C
?
A
/
S
/
L and
?
C
?
A
/
S
?
H inputs internally generate a
?
C
?
A
/
S
signal functioning in a similar manner to the single
?
C
?
A
/
S input of other DRAMs. The key difference is each
?
C
?
A
/
S input (
?
C
?
A
/
S
/
L and
?
C
?
A
/
S
?
H ) controls its corresponding
8 DQ inputs during WRITE accesses.
?
C
?
AS
/
L controls DQ1
/
through DQ8 and
?
C
?
AS
?
H controls DQ9 through DQ16. The
/
two
?
C
?
AS controls give the MT4LC1M16E5(S) both BYTE
/
READ and BYTE WRITE cycle capabilities.
A logic HIGH on
?
WE dictates READ mode while a logic
/
LOW on WE dictates WRITE mode. During a WRITE cycle,
? /
data-in (D) is latched by the falling edge of WE or
?
C
?
A
/
S
(?C
?
AS
/
L or
?
C
?
AS
/
H), whichever occurs last. An EARLY WRITE
/
/
occurs when WE is taken LOW prior to either
?
C
?
A
/
S falling.
A LATE WRITE or READ-MODIFY-WRITE occurs when
WE falls after
?
C
?
A
/
S (?C
?
A
/
S
/
L or
?
C
?
A
/
S
/
H) was taken LOW.
During EARLY WRITE cycles, the data-outputs (Q) will
remain High-Z regardless of the state of
?
O
/
E. During LATE
WRITE or READ-MODIFY-WRITE cycles,
?
O
/
E must be
taken HIGH to disable the data-outputs prior to applying
input data. If a LATE WRITE or READ-MODIFY-WRITE is
attempted while keeping
?
O
/
E LOW, no write will occur, and
the data-outputs will drive read data from the accessed
location.
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O. Pin direction is controlled by
?
OE and
?
WE.
/
/
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-address-
defined page boundary. The PAGE cycle is always initiated
with a row-address strobed-in by R
?
A
/
S followed by a col-
?
umn-address strobed-in by C
?
A
/
S.
?
C
?
A
/
S may be toggled-in
?
by holding
?
R
?
A
/
S LOW and strobing-in different column-
addresses, thus executing faster memory cycles. Returning
?
R
?
A
/
S HIGH terminates the PAGE MODE of operation.
EDO PAGE MODE
The AS4LC1M16 provides EDO PAGE MODE which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
?
C
?
A
/
S returns HIGH. EDO provides for
?
C
?
A
/
S precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of
?
C
?
A
/
S output control provides for pipeline
READs.
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
?
C
?
A
/
S. EDO-PAGE-MODE DRAMs operate similar to
FAST-PAGE-MODE DRAMs, except data will remain valid
or become valid after
?
C
?
A
/
S goes HIGH during READs,
provided
?
R
?
A
/
S and
?
O
/
E are held LOW. If
?
O
/
E is pulsed while
?
R
?
A
/
S and
?
C
?
A
/
S are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If
?
O
/
E is toggled or
pulsed after
?
C
?
A
/
S goes HIGH while
?
R
?
A
/
S remains LOW, data
will transition to and remain High-Z (refer to Figure 1).
RAS
V IH
V IL
CASL/CASH
ADDR
DQ V IOH
V IOL
,, ,,, ,,,,, ,,,,, ,,,,, ,,,,
,
,, , , ,
V IH
V IL
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
OPEN
V IH
V IL
OE
,,
VALID DATA (A)
t OD
VALID DATA (A)
t OES
t OE
,,, ,,
VALID DATA (B)
t OD
t OEHC
VALID DATA (C)
t OD
,
VALID DATA (D)
t OEP
The DQs go back to
Low-Z if
t
OES is met.
The DQs remain High-Z
until the next CAS cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS cycle
if
t
OEP is met.
Figure 1
OUTPUT ENABLE AND DISABLE
AS4LC1M16
REV. 3/97
DS000020
,
,
,,
,,
DON’T CARE
UNDEFINED
2-94
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
EDO PAGE MODE
(continued)
?
W
/
E can also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.
During an application, if the DQ outputs are wire OR’d,
?
O
/
E must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing
?
W
/
E to the idle banks during
?
C
?
A
/
S HIGH time
will also High-Z the outputs. Independent of
?
O
/
E control,
the outputs will disable after
t
OFF, which is referenced
from the rising edge of
?
R
?
A
/
S or
?
C
?
A
/
S, whichever occurs last.
RAS
CASL/CASH
ADDR
DQ V IOH
V IOL
, ,,,,,, ,,, , ,,,,
,, ,,
,
,
, , , ,
,,
,,
,
V IH
V IL
V IH
V IL
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
OPEN
V IH
V IL
V IH
V IL
WE
,,
VALID DATA (A)
t WHZ
t WPZ
,
VALID DATA (B)
INPUT DATA (C)
t WHZ
,,
OE
The DQs go to High-Z if WE falls, and if
t
WPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
Figure 2
?
W
/
E CONTROL OF DQs
,,
,,
,
,,
DON’T CARE
UNDEFINED
AS4LC1M16
REV. 3/97
DS000020
2-95
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined by
the use of
?
C
?
A
/
S
/
L and
?
C
?
A
/
S
?
H. Enabling
?
C
?
A
/
S
/
L will select a
lower BYTE access (DQ1-DQ8). Enabling
?
C
?
A
/
S
?
H will select
an upper BYTE access (DQ9-DQ16). Enabling both
?
C
?
A
/
S
/
L
and
?
C
?
A
/
S
?
H selects a WORD WRITE cycle.
The AS4LC1M16 may be viewed as two 1 Meg x 8
DRAMs that have common input controls, with the excep-
tion of the
/ ?
C
?
A
/
S inputs. Figure 3 illustrates the BYTE WRITE
and WORD WRITE cycles.
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A
?
C
?
A
/
S precharge
must be satisfied prior to changing modes of operation
between the upper and lower bytes. For example, an EARLY
WRITE on one byte and a LATE WRITE on the other byte is
not allowed during the same cycle. However, an EARLY
WRITE on one byte and, after a
?
C
?
A
/
S precharge has been
satisfied, a LATE WRITE on the other byte is permissable.
REFRESH
Preserve correct memory cell data by maintaining power
and executing a
?
R
?
A
/
S cycle (READ, WRITE) or
?
R
?
A
/
S refresh
cycle (?R
?
A
/
S ONLY, CBR, or HIDDEN) so that all 1,024
combinations of RAS addresses are executed at least every
? ? /
16ms, regardless of sequence. The CBR REFRESH cycle will
invoke the refresh counter for automatic
?
R
?
A
/
S addressing.
WORD WRITE
RAS
LOWER BYTE WRITE
CASL
CASH
WE
STORED
DATA
1
1
0
INPUT
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
STORED STORED
DATA
DATA
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
LOWER BYTE
(DQ1-DQ8)
OF WORD
1
1
1
1
1
UPPER BYTE
(DQ9-DQ16)
OF WORD
0
1
0
1
0
0
0
0
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
ADDRESS 1
1
0
1
0
1
1
1
1
ADDRESS 0
X = NOT EFFECTIVE (DON'T CARE)
Figure 3
WORD AND BYTE WRITE EXAMPLE
AS4LC1M16
REV. 3/97
DS000020
2-96
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
WE
CASL
CASH
DQ1
16
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
10
CAS
DATA-IN BUFFER
DQ16
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
10
COLUMN-
ADDRESS
BUFFER
REFRESH
CONTROLLER
COLUMN
DECODER
16
1024
OE
16
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
10
ROW-
ADDRESS
BUFFERS (10)
ROW
DECODER
1024 x 1024 x 16
MEMORY
ARRAY
1024 x 16
10
1024
RAS
NO. 1 CLOCK
GENERATOR
Vcc
Vss
AS4LC1M16
REV. 3/97
DS000020
2-97
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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