3959
A3959SLB
CP
CP
2
CP
1
PHASE
ROSC
GROUND
GROUND
LOGIC SUPPLY
ENABLE
PFD
2
BLANK
PFD
1
DMOS FULL-BRIDGE PWM
MOTOR DRIVER
CHARGE PUMP
1
2
3
4
5
θ
24
23
NC
22
21
V
BB
20
19
18
V
DD
17
16
V
REG
SLEEP
NO
CONNECTION
OUT
B
LOAD SUPPLY
GROUND
GROUND
SENSE
OUT
A
NO
CONNECTION
EXT MODE
REF
Designed for pulse-width modulated (PWM) current control of dc
motors, the A3959SB and A3959SLB are capable of output currents to
±3
A and operating voltages to 50 V. Internal fixed off-time PWM
current-control timing circuitry can be adjusted via control inputs to
operate in slow, fast, and mixed current-decay modes.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM-control signals. Internal synchronous rectification
control circuitry is provided to reduce power dissipation during PWM
operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of supply and charge pump, and
crossover-current protection. Special power-up sequencing is not
required.
The A3959SB/SLB is supplied in a choice of two power
packages, a 24-pin plastic DIP with a copper batwing tab (package
suffix ‘B’), and a 24-lead plastic SOIC with a copper batwing tab
(package suffix ‘LB’). In both cases, the power tab is at ground
potential and needs no electrical isolation.
Data Sheet
29319.37*
6
7
8
9
9
LOGIC
PWM TIMER
10
11
12
NC
15
14
÷
10
13
Dwg. PP-069-4
Note that the A3959SLB(SOIC) and A3959SB
(DIP) do not share a common terminal
assignment.
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, V
BB
.........................
50 V
Output Current, I
OUT
(Repetitive) ...........
±
3.0 A
(Peak, <3
µs)
...................................
±
6.0 A
Logic Supply Voltage, V
DD
.......................
7.0 V
Logic Input Voltage Range, V
IN
(Continuous) ............
-0.3 V to V
DD
+ 0.3 V
(t
w
<30 ns) ...............
-1.0 V to V
DD
+ 1.0 V
Sense Voltage, V
S
(Continuous) ..............
0.5 V
(t
w
<3
µs)
...........................................
2.5 V
Reference Voltage, V
REF
............................
V
DD
Package Power Dissipation (T
A
= 25°C), P
D
A3959SB ........................................
3.1 W*
A3959SLB ......................................
2.2 W*
Operating Temp. Range, T
A
....
-20
°
C to +85
°
C
Junction Temperature, T
J
.....................
+150
°
C
Storage Temp. Range, T
S
.....
-55
°
C to +150
°
C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified
current rating or a junction temperature of 150°C.
* Per SEMI G42-88 Specification.
FEATURES
s
s
s
s
s
s
s
±3
A, 50 V Output Rating
Low
r
DS(on)
Outputs (270 mΩ, Typical)
Mixed, Fast, and Slow Current-Decay Modes
Synchronous Rectification for Low Power Dissipation
Internal UVLO and Thermal-Shutdown Circuitry
Crossover-Current Protection
Internal Oscillator for Digital PWM Timing
Always order by complete part number:
Part Number
A3959SB
A3959SLB
Package
24-pin batwing DIP
24-lead batwing SOIC
R
θJA
40°C/W
56°C/W
R
θJT
6°C/W
6°C/W
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
V
DD
LOGIC
SUPPLY
CHARGE PUMP
BANDGAP
V
DD
C
REG
TSD
V
BB
+
CP1
CP2
LOAD
SUPPLY
BANDGAP
REGULATOR
V
REG
UNDER-
VOLTAGE &
FAULT DETECT
CHARGE
PUMP
SLEEP
EXT MODE
PHASE
ENABLE
CONTROL LOGIC
GATE DRIVE
CP
OUT
A
OUT
B
SENSE
BLANK
PFD1
PFD2
ROSC
OSC
PWM
TIMER
ZERO
CURRENT
DETECT
C
S
R
S
CURRENT
SENSE
REFERENCE
BUFFER &
÷10
REF
V
REF
Dwg. FP-048-2
CP
2
CP
1
PHASE
ROSC
GROUND
GROUND
GROUND
GROUND
LOGIC
SUPPLY
ENABLE
PFD
2
BLANK
1
2
3
4
5
θ
CHARGE PUMP
24
23
22
21
V
BB
20
19
18
17
CP
V
REG
SLEEP
OUT
B
LOAD
SUPPLY
GROUND
GROUND
SENSE
OUT
A
EXT MODE
REF
PFD
1
Dwg. PP-069-5
A3959SB
Note that the A3959SLB (SOIC) and A3959SB
(DIP) do not share a common terminal
assignment.
6
7
8
9
9
10
11
12
V
DD
LOGIC
16
15
÷
10
PWM TIMER
14
13
2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright ' 2001 Allegro MicroSystems, Inc.
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise)
Limits
Characteristics
Output Drivers
Load Supply Voltage Range
Output Leakage Current
Output On Resistance
Crossover Delay
Body Diode Forward Voltage
Load Supply Current
V
F
I
BB
Source diode, I
F
= -3 A
Sink diode, I
F
= 3 A
f
PWM
< 50 kHz
Charge pump on, outputs disabled
Sleep Mode
Control Logic
Logic Supply Voltage Range
Logic Input Voltage
Logic Input Current
(all inputs except ENABLE)
ENABLE Input Current
Internal OSC frequency
Reference Input Volt. Range
Reference Input Current
Comparator Input Offset Volt.
V
DD
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
I
IN(1)
I
IN(0)
f
OSC
V
REF
I
REF
V
IO
V
IN
= 2.0 V
V
IN
= 0.8 V
V
IN
= 2.0 V
V
IN
= 0.8 V
R
OSC
= 0
Ω
R
OSC
= 51 kΩ
Operating
V
REF
= V
DD
V
REF
= 0 V
Operating
4.5
2.0
—
-20
—
—
—
3.25
3.65
0.0
—
—
5.0
—
—
<1.0
<-2.0
40
16
4.25
4.25
—
—
±5.0
5.5
—
0.8
20
-20
100
40
5.25
4.85
V
DD
±1.0
—
V
V
V
µA
µA
µA
µA
MHz
MHz
V
µA
mV
V
BB
I
DSS
r
DS(on)
Operating
During sleep mode
V
OUT
= V
BB
V
OUT
= 0 V
Source driver, I
OUT
= -3 A
Sink driver, I
OUT
= 3 A
9.5
0
—
—
—
—
300
—
—
—
—
—
—
—
<1.0
<-1.0
270
270
600
—
—
4.0
2.0
—
50
50
20
-20
300
300
1000
1.6
1.6
7.0
5.0
20
V
V
µA
µA
mΩ
mΩ
ns
V
V
mA
mA
µA
Symbol Test Conditions
Min. Typ. Max.
Units
Continued next page …
www.allegromicro.com
3
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise), continued.
Limits
Characteristics
Control Logic
Reference Divider Ratio
G
m
Error
(Note 3)
Propagation Delay Times
t
pd
—
E
Gm
V
REF
= V
DD
V
REF
= 0.5 V
0.5 E
in
to 0.9 E
out
:
PWM change to source on
PWM change to source off
PWM change to sink on
PWM change to sink off
—
—
—
600
50
600
50
—
—
Increasing V
DD
f
PWM
< 50 kHz
Sleep Mode
3.90
0.05
—
—
10
—
—
750
150
750
100
165
15
4.2
0.10
6.0
—
—
±4.0
±14
1200
350
1200
150
—
—
4.45
—
10
2.0
—
%
%
ns
ns
ns
ns
°C
°C
V
V
mA
mA
Symbol Test Conditions
Min. Typ. Max.
Units
Thermp Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
Logic Supply Current
T
J
∆T
J
UVLO
∆UVLO
I
DD
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. G
m
error = ([V
REF
/10] – V
SENSE
)/(V
REF
/10) where
V
SENSE
= I
TRIP
•R
S
.
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
V
REG
.
This internally generated voltage is used to operate
the sink-side DMOS outputs. The V
REG
terminal should
be decoupled with a 0.22
µF
capacitor to ground. V
REG
is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
Charge Pump.
The charge pump is used to generate a
gate-supply voltage greater than V
BB
to drive the source-
side DMOS gates. A 0.22
µF
ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes.
A 0.22
µF
ceramic capacitor should be connected between
CP and V
BB
to act as a reservoir to operate the high-side
DMOS devices. The CP voltage is internally monitored
and, in the case of a fault condition, the source outputs of
the device are disabled.
PHASE Logic.
The PHASE input terminal determines if
the device is operating in the “forward” or “reverse” state.
PHASE
0
1
OUT
A
Low
High
OUT
B
High
Low
EXT MODE Logic.
When using external PWM current
control, the EXT MODE input determines the current path
during the chopped cycle. With EXT MODE low, fast
decay mode, the opposite pair of selected outputs will be
enabled during the off cycle. With EXT MODE high,
slow decay mode, both sink drivers are on with ENABLE
low.
EXT MODE
0
1
Decay
Fast
Slow
Current Regulation.
Load current is regulated by an
internal fixed off-time PWM control circuit. When the
outputs of the DMOS H bridge are turned on, the current
increases in the motor winding until it reaches a trip value
determined by the external sense resistor (R
S
) and the
applied analog reference voltage (V
REF
):
I
TRIP
= V
REF
/10R
S
At the trip point, the sense comparator resets the source-
enable latch, turning off the source driver. The load
inductance then causes the current to recirculate for the
fixed off-time period. The current path during
recirculation is determined by the configuration of slow/
mixed/fast current-decay mode via PFD1 and PFD2.
Oscillator.
The PWM timer is based on an internal
oscillator set by a resistor connected from the OSC
terminal to V
DD
. Typical value of 4 MHz is set with a
51 kΩ resistor. The allowable range of the resistor is from
20 kΩ to 100 kΩ.
f
OSC
= 204 x 10
9
/R
OSC
.
Fixed Off Time.
The A3959 is set for a fixed off time of
96 cycles of the internal oscillator, typically 24
µs
with a
4 MHz oscillator.
ENABLE Logic.
The ENABLE input terminal allows
external PWM. ENABLE high turns on the selected sink-
source pair. ENABLE low switches off the source driver
or the source and sink driver, depending on EXT MODE,
and the load current decays. If ENABLE is kept high, the
current will rise until it reaches the level set by the internal
current-control circuit.
ENABLE
0
1
Outputs
Chopped
On
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5
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