DATASHEET
VCXO AND HDTV SET-TOP CLOCK SOURCE
Description
The MK3771-17 is a low cost, low jitter, high-perfomance
VCXO and clock synthesizer designed for set-top boxes and
HDTV receivers. The on-chip Voltage Controlled Crystal
Oscillator accepts a 0 to 3.3 V input voltage to cause the
output clocks to vary by ±100 ppm. Using IDT’s patented
VCXO and analog Phase-Locked Loop (PLL) techniques,
the device uses an inexpensive 13.5 MHz crystal input to
produce multiple output clocks including selectable BCLK, a
selectable audio clock, two communications clocks, a 13.5
MHz clock, and three 27 MHz clocks. All clocks are
frequency locked to the 27 MHz output (and to each other)
with zero ppm error, so any output can be used as the VCXO
output.
MK3771-17
Features
•
•
•
•
•
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Packaged in 28-pin SSOP
Pb (lead) free package
HDTV frequencies of 74.25 and 74.175824 MHz
On-chip patented VCXO with pull range of 200 ppm
(minimum)
VCXO tuning voltage of 0 to 3.3 V
Supports Ethernet with 20 and 25 MHz clocks
Modem clocks of 11.0592 and 24.576 MHz option
Audio clocks support 32 kHz, 44.1 kHz, 48 kHz and 96
kHz sampling rates
27MHz VCXO)
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Zero ppm synthesis error in all clocks (all exactly track
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Uses an inexpensive 13.5 MHz crystal
Full CMOS output swings with 12 mA output
drive capability at TTL levels
Advanced, low power, sub-micron CMOS process
3.3 V ±5% operating supply
Block Diagram
AS2:0
BS1, BS0
CS
VIN
3
2
Audio Clock
PLL Clock
Synthesis
Circuitry
BCLK
CCLK1
CCLK2
XI
13.5 MHz
pullable crystal
XO
Voltage
Controlled
Crystal
Oscillator
X8
PLL
Divide
Logic
108 MHz or 27 MHz
54 MHz or 27 MHz
27 MHz
13.5 MHz or 27 MHz
VS
IDT™
VCXO AND HDTV SET-TOP CLOCK SOURCE
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MK3771-17
REV E 051310
MK3771-17
VCXO AND HDTV SET-TOP CLOCK SOURCE
VCXO AND SYNTHESIZER
Pin Descriptions
Pin
Number
1
2
3
4, 5, 7, 8, 22
6
9
10, 11, 19,
20, 24
12
13
14
15
16
17
18
21
23
25
26
27
28
Pin
Name
BS0
X2
X1
VDD
VIN
CS
GND
BCLK
VS
ACLK
CCLK2
BS1
CCLK1
VCLK3
AS2
VCLK4
VCLK1
VCLK2
AS0
AS1
Pin
Type
I
XO
XI
P
I
TI
P
O
TI
O
O
TI
O
O
I
O
O
O
I
I
B clock select 0.
Pin Description
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Connect to +3.3 V.
Analog control voltage for VCXO. Pulls outputs ±100 ppm by varying from
0 to 3.3 V.
Communications Clock Select. Selects CCLK 1 and 2 per table above.
Internal pull-up.
Connect to ground.
B clock output. Determined by status of AS2:0 per table above.
VCXO Clock Select. Selects frequencies on VCLK1-VCLK4 per table
above.
Audio Clock Output. Determined by status of AS2:0 per table above.
Communications Clock Output 2. Determined by status of CS per table
above.
B Clock Select 1. Selects BCLK frequency. See table above.
Communications Clock Output 1. Determined by status of CS per table
above.
VCXO Clock output 3. Can be either 27 or 13.5 MHz per table above.
Audio Clock Select pin 2. Selects Audio clock on pin 14 per table above.
Internal pull-up.
VCXO Clock output 4. Can be either 27 or 108 MHz per table above.
VCXO Clock output 1. Always 27 MHz.
VCXO Clock output 2. Can be either 27 or 54 MHz per table above.
Audio Clock Select pin 0. Selects Audio clock on pin 14 per table above.
Internal pull-up.
Audio Clock Select pin 1. Selects Audio clock on pin 14 per table above.
Internal pull-up.
KEY:
I = Input
TI = Tri-level
O = Output
P = Power supply connection
XI, XO= Crystal connections
IDT™
VCXO AND HDTV SET-TOP CLOCK SOURCE
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MK3771-17
REV E 051310
MK3771-17
VCXO AND HDTV SET-TOP CLOCK SOURCE
VCXO AND SYNTHESIZER
External Component Selection
The MK3771-17 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01µF should be connected
between VDD and GND on pins 3 and 6, and on pins 13 and
14, as close to the MK3771-17 as possible. For optimum
device performance, the decoupling capacitors should be
mounted on the component side of the PCB. Avoid the use
of vias in the decoupling circuit.
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on the
PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of your final
layout, a frequency counter capable of about 1 ppm
resolution and accuracy, two power supplies, and some
samples of the crystals which you plan to use in production,
along with measured initial accuracy for each crystal at the
specified crystal load capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3771-17 to 3.3 V. Connect pin 4
of the MK3771-17 to the second power supply. Adjust the
voltage on pin 4 to 0V. Measure and record the frequency of
the CLK output.
2. Adjust the voltage on pin 4 to 3.3 V. Measure and record
the frequency of the same output.
To calculate the centering error:
Series Termination Resistor
When the PCB traces between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω
.
Quartz Crystal
The MK3771-17 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To assure
the best system performance (frequency pull range) and
reliability, a crystal device with the recommended
parameters must be used, and the layout guidelines
discussed in the following section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
MK3771-17 incorporates on-chip variable load capacitors
that “pull” (change) the frequency of the crystal. The crystal
specified for use with the MK3771-17 is designed to have
zero frequency error when the total of on-chip + stray
capacitance is 14 pF.
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the MK3771-17. There should be no vias between the
crystal pins and the X1 and X2 device pins. There should be
no signal traces underneath or close to the crystal.
Please see application note MAN05 for recommended
crystal parameters and suppliers.
6
(
f
3.3V
–
f
t arg et
)
+
(
f
0V
–
f
t arg et
)
-
Error = 10 x -----------------------------------------------------------------------------
–
error
xtal
f
t arg et
Where:
f
target
= nominal crystal frequency
error
xtal
=actual initial accuracy (in ppm) of the crystal being
measured
If the centering error is less than ±25 ppm, no adjustment is
needed. If the centering error is more than 25ppm negative,
the PC board has excessive stray capacitance and a new
PCB layout should be considered to reduce stray
capacitance. (Alternately, the crystal may be re-specified to
a higher load capacitance. Contact IDT for details.) If the
centering error is more than 25ppm positive, add identical
fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
IDT™
VCXO AND HDTV SET-TOP CLOCK SOURCE
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MK3771-17
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VCXO AND HDTV SET-TOP CLOCK SOURCE
VCXO AND SYNTHESIZER
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by your
crystal vendor. If you do not know the value, assume it is 30
ppm/pF. After any changes, repeat the measurement to
verify that the remaining error is acceptably low (typically
less than ±25ppm).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3771-17. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.15
Typ.
+3.3
Max.
+70
+3.45
Units
°
C
V
IDT™
VCXO AND HDTV SET-TOP CLOCK SOURCE
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MK3771-17
REV E 051310
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