FIN1101 LVDS Single Port High Speed Repeater
January 2002
Revised September 2002
FIN1101
LVDS Single Port High Speed Repeater
General Description
This single port repeater is designed for high speed inter-
connects utilizing Low Voltage Differential Signaling
(LVDS) technology. It accepts and outputs LVDS levels
with a typical differential output swing of 330 mV which pro-
vides low EMI at ultra low power dissipation even at high
frequencies. It can directly accept multiple differential I/O
including: LVPECL, HSTL, and SSTL-2 for translating
directly to LVDS.
Features
s
Up to 1.6 Gb/s full differential path
s
3.5 ps max random jitter and 135 ps max deterministic
jitter
s
3.3V power supply operation
s
Wide rail-to-rail common mode range
s
Ultra low power consumption
s
LVDS receiver inputs accept LVPECL, HSTL, and
SSTL-2 directly
s
Power off protection
s
7 kV HBM ESD protection (all pins)
s
Meets or exceed the TA/EIA-644-A LVDS standard
s
Packaged in 8-pin SOIC and US8
s
Open circuit fail safe protection
Ordering Code:
Order Number
FIN1101M
FIN1101MX
FIN1101K8X
Package Number
M08A
M08A
MAB08A
Package Description
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
Connection Diagrams
SOIC Package
Pin Descriptions
Pin Name
R
IN+
R
IN−
D
OUT+
D
OUT−
EN
V
CC
Description
Non-Inverting LVDS Inputs
Inverting LVDS Inputs
Non-Inverting Driver Outputs
Inverting Driver Outputs
Driver Enable Pin
Power Supply
Ground
US8 Package
GND
Function Table
Inputs
EN
H
H
H
L
H
=
HIGH Logic Level
X
=
Don’t Care
Outputs
R
IN−
L
H
X
D
OUT+
H
L
H
Z
D
OUT−
L
H
L
Z
R
IN+
H
L
X
Functional Diagram
Fail Safe Case
L
=
LOW Logic Level
Z
=
High Impedance
© 2002 Fairchild Semiconductor Corporation
DS500654
www.fairchildsemi.com
FIN1101
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
LVDS DC Input Voltage (V
IN
)
LVDS DC Output Voltage (V
OUT
)
Driver Short Circuit Current (I
OSD
)
Storage Temperature Range (T
STG
)
Max Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Machine Model)
260
°
C
7000V
300V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
Continuous 10 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Operating Temperature (T
A
)
Magnitude of Input
Differential Voltage (|V
ID
|)
Common Mode Input Voltage
(V
IC
)
(0V
+
|V
ID
|/2) to (V
CC
−
|V
ID
|/2)
100 mV to V
CC
3.0V to 3.6V
−
40
°
C to
+
85
°
C
−
65
°
C to
+
150
°
C
150
°
C
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
V
TH
V
TL
V
IH
V
IL
V
OD
∆V
OD
V
OS
∆V
OS
I
OS
I
IN
I
OFF
I
CCZ
I
CC
I
OZ
V
IC
C
IN
C
OUT
Parameter
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input High Voltage (EN)
Input Low Voltage (EN)
Output Differential Voltage
V
OD
Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
Offset Magnitude Change from
Differential LOW-to-HIGH
Short Circuit Output Current
Input Current (EN, D
INX
+
, D
INX
−
)
D
OUT
+
=
0V & D
OUT
−
=
0V, Driver Enabled
V
OD
=
0V, Driver Enabled
V
IN
=
0V to V
CC
,
Other Input
=
V
CC
or 0V (for Differential Inputs)
Power-Off Input or Output Current V
CC
=
0V, V
IN
or V
OUT
=
0V to 3.6V
Disabled Power Supply Current
Power Supply Current
Drivers Disabled
Drivers Enabled, Any Valid Input Condition
D
OUT
−
=
0V to 3.6V
Common Mode Voltage Range
Input Capacitance
Output Capacitance
|V
ID
|
=
100 mV to V
CC
EN Input
Data Input
0V
+
|V
ID|
/2
2.2
2.0
2.6
3.2
9.3
−3.4
±3.4
R
L
=
100
Ω,
Driver Enabled,
See Figure 2
1.125
1.23
Test Conditions
See Figure 1; V
IC
= +0.05V, +1.2V,
or (V
CC
−
0.05V)
See Figure 1; V
IC
= +0.05V, +1.2V,
or (V
CC
−
0.05V)
−100
2.0
GND
250
330
V
CC
0.8
450
25
1.375
25
−6
±6
±20
±20
5.5
13.5
±20
V
CC
−
(|V
ID
|/2)
Min
Typ
(Note 2)
100
Max
Units
mV
mV
V
V
mV
mV
V
mV
mA
mA
µA
µA
mA
mA
µA
V
pF
pF
Disabled Output Leakage Current Driver Disabled, D
OUT
+
=
0V to 3.6V or
Note 2:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
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FIN1101
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLHD
t
PHLD
t
TLHD
t
THLD
t
SK(P)
t
SK(PP)
f
MAX
t
PZHD
t
PZLD
t
PHZD
t
PLZD
t
DJ
t
RJ
Parameter
Differential Propagation Delay
LOW-to-HIGH
Differential Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Part-to-Part Skew (Note 4)
Maximum Frequency (Note 5)(Note 6)
Differential Output Enable Time from Z to HIGH
Differential Output Enable Time from Z to LOW R
L
=
100
Ω,
C
L
=
5 pF,
Differential Output Disable Time from HIGH to Z See Figure 2 and Figure 3
Differential Output Disable Time from LOW to Z
LVDS Data Jitter,
Deterministic
LVDS Clock Jitter, Random
(RMS)
V
ID
=
300 mV, PRBS
=
2
23
−
1,
V
IC
=
1.2V at 800 Mbps
V
ID
=
300 mV
V
IC
=
1.2 V at 400 MHz
400
800
2.1
2.3
1.5
1.8
85
2.1
5
5
5
5
135
3.5
R
L
=
100
Ω,
C
L
=
5 pF,
V
ID
=
200 mV to 450 mV,
V
IC
=
|V
ID
|/2 to (V
CC
−
(V
ID
/2),
Duty Cycle
=
50%,
See Figure 3 and Figure 4
Test Conditions
Min
Typ
(Note 3)
0.75
0.75
0.29
0.29
1.1
1.1
0.40
0.40
0.01
1.75
1.75
0.58
0.58
0.2
0.5
Max
Units
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ps
ps
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V, V
ID
=
300mV, V
IC
=
1.2V unless otherwise specified.
Note 4:
t
SK(PP)
is the magnitude of the difference in differential propagation delay times between identical channels of two devices switching in the same
direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test cir-
cuits.
Note 5:
Passing criteria for maximum frequency is the output V
OD
>
200 mV and the duty cycle is 45% to 55% with all channels switching.
Note 6:
Output loading is transmission line environment only; C
L
is
<
1 pF of stray test fixture capacitance.
FIGURE 1. Differential Receiver Voltage Definitions and
Propagation I and Transition Time Test Circuit
FIGURE 2. Differential Driver DC Test Circuit
Note A: All LVDS input pulses have frequency
=
10MHz, t
R
or t
F
< =
0.5 ns
Note B: C
L
includes all probe and test fixture capacitances
FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit
3
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FIN1101
FIGURE 4. AC Waveforms
Note A: All LVTTL input pulses have frequency
=
10 MHz, t
R
or t
F
< =
2 ns
Note B: C
L
includes all probe and test fixture capacitances
FIGURE 5. Differential Driver Enable and Disable Test Circuit
FIGURE 6. Enable and Disable AC Waveforms
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4
FIN1101
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M08A
5
www.fairchildsemi.com
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