FIN1025 3.3V LVDS 2-Bit High Speed Differential Driver
June 2002
Revised June 2002
FIN1025
3.3V LVDS 2-Bit High Speed Differential Driver
General Description
This dual driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The driver translates LVTTL signal levels to LVDS lev-
els with a typical differential output swing of 350mV which
provides low EMI at ultra low power dissipation even at
high frequencies. This device is ideal for high speed trans-
fer of clock and data.
The FIN1025 can be paired with its companion receiver,
the FIN1026, or any other LVDS receiver.
Features
s
Greater than 400Mbs data rate
s
Flow-through pinout simplifies PCB layout
s
3.3V power supply operation
s
0.4ns maximum differential pulse skew
s
1.7ns maximum propagation delay
s
Low power dissipation
s
Power-Off protection
s
Meets or exceeds the TIA/EIA-644 LVDS standard
s
14-Lead TSSOP package saves space
Ordering Code:
Order Number
FIN1025MTC
Package Number
MTC14
Package Description
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
D
IN1
, D
IN2
,
D
OUT1+
, D
OUT2+
D
OUT1−
, D
OUT2−
EN
EN
V
CC
GND
NC
Description
LVTTL Data Inputs
Non-Inverting Driver Outputs
Inverting Driver Outputs
Driver Enable Pin
Inverting Driver Enable Pin
Power Supply
Ground
No Connect
Truth Table
Inputs
EN
H
H
H
X
L or OPEN
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don’t Care
Z
=
High Impedance
Outputs
D
IN
H
L
OPEN
X
X
D
OUT+
H
L
L
Z
Z
D
OUT−
L
H
H
Z
Z
EN
L or OPEN
L or OPEN
L or OPEN
H
X
© 2002 Fairchild Semiconductor Corporation
DS500783
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FIN1025
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
LVTTL DC Input Voltage (V
IN
)
LVDS DC Output Voltage (V
OUT
)
Driver Short Circuit Current (I
OSD
)
Storage Temperature Range (T
STG
)
Max Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Machine Model)
10,000V
600V
−
0.5V to
+
4.6V
−
0.5V to
+
6V
−
0.5V to 4.6V
Continuous
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Operating Temperature (T
A
)
3.0V to 3.6V
0 to V
CC
−
40
°
C to
+
85
°
C
−
65
°
C to
+
150
°
C
150
°
C
260
°
C
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
V
OH
V
OL
I
OFF
I
OS
V
IH
V
IL
I
IN
I
OZ
I
I(OFF)
V
IK
I
CC
Parameter
Output Differential Voltage
V
OD
Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
Offset Magnitude Change from
Differential LOW-to-HIGH
HIGH Output Voltage
LOW Output Voltage
Power Off Output Current
Short Circuit Output Current
Input HIGH Voltage
Input LOW Voltage
Input Current
Disabled Output Leakage Current
Power-Off Input Current
Input Clamp Voltage
Power Supply Current
V
IN
=
0V or V
CC
V
OUT
=
0V or 3.6V
V
CC
=
0V, V
IN
=
0V or 3.6V
I
IK
= −18
mA
No Load, V
IN
=
0V or V
CC
, Driver Enabled
R
L
=
100
Ω,
Driver Disabled
R
L
=
100
Ω,
V
IN
=
0V or V
CC
, Driver Enabled
Note 2:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
Test Conditions
Min
250
Typ
(Note 2)
340
1.4
Max
450
25
1.375
25
1.6
20
Units
mV
mV
V
mV
V
V
µA
mA
V
V
µA
µA
µA
V
R
L
=
100Ω, Driver Enabled,
See Figure 1
1.125
1.25
1.2
V
IN
=
V
CC
, R
L
=
100Ω
V
IN
=
0V, R
L
=
100Ω
V
CC
=
0V, V
OUT
=
0V or 3.6V
V
OUT
=
0V, Driver Enabled
V
OD
=
0V, Driver Enabled
2.0
GND
−20
−20
−20
−1.5
0.9
−20
1.4
1.05
−3
−3.5
−6
−6
V
CC
0.8
20
20
20
−0.8
5
1.7
9
8
4
16
mA
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2
FIN1025
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLHD
t
PHLD
t
TLHD
t
THLD
t
SK(P)
t
SK(LH)
t
SK(HL)
t
SK(PP)
f
MAX
t
ZHD
t
ZLD
t
HZD
t
LZD
C
IN
C
OUT
Parameter
Differential Propagation Delay
LOW-to-HIGH
Differential Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency (Note 6)
Differential Output Enable Time from Z to HIGH
Differential Output Enable Time from Z to LOW R
L
=
100Ω, C
L
=
10 pF,
Differential Output Disable Time from HIGH to Z See Figure 4 (Note 7), and Figure 5
Differential Output Disable Time from LOW to Z
Input Capacitance
Output Capacitance
R
L
=
100Ω, See Figure 6 (Note 7)
200
250
1.7
1.7
2.7
2.7
4.2
5.2
5.0
5.0
5.0
5.0
0.05
R
L
=
100
Ω,
C
L
=
10 pF,
See Figure 2 (Note 7), and Figure 3
Test Conditions
Min
Typ
(Note 3)
0.6
0.6
0.4
0.4
1.1
1.2
1.7
1.7
1.2
1.2
0.4
0.3
1.0
Max
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
pF
pF
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
f
MAX
criteria: Input t
R
=
t
F
<
1ns, 0V to 3V, 50% Duty Cycle; Output V
OD
>
250 mv, 45% to 55% Duty Cycle; all switching in phase channels.
Note 7:
Test Circuits in Figures 2, 4, 6 are simplified representations of test fixture and DUT loading.
3
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FIN1025
Note A:
All input pulses have frequency
=
10 MHz, t
R
or t
F
=
1 ns
Note B:
C
L
includes all fixture and instrumentation capacitance
FIGURE 1. Differential Driver DC Test Circuit
FIGURE 2. Differential Driver Propagation Delay and
Transition Time Test Circuit
Note B:
All input pulses have the frequency
=
10 MHz, t
R
or t
F
=
1 ns
Note A:
C
L
includes all fixture and instrumentation capacitance
FIGURE 3. AC Waveforms
FIGURE 4. Differential Driver Enable and
Disable Test Circuit
FIGURE 5. Enable and Disable AC Waveforms
FIGURE 6. f
MAX
Test Circuit
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4
FIN1025
DC / AC Typical Performance Curves
FIGURE 7. Output High Voltage vs.
Power Supply Voltage
FIGURE 8. Output Low Voltage vs.
Power Supply Voltage
FIGURE 9. Output Short Circuit Current vs.
Power Supply Voltage
FIGURE 10. Differential Output Voltage vs.
Power Supply Voltage
FIGURE 11. Differential Output Voltage vs.
Load Resistor
FIGURE 12. Offset Voltage vs.
Power Supply Voltage
5
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