FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver
June 2002
Revised June 2002
FIN1026
3.3V LVDS 2-Bit High Speed Differential Receiver
General Description
This dual receiver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The receiver translates LVDS levels, with a typical dif-
ferential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
The FIN1026 can be paired with its companion driver, the
FIN1025, or any other LVDS driver.
Features
s
Greater than 400Mbs data rate
s
Flow-through pinout simplifies PCB layout
s
3.3V power supply operation
s
0.4ns maximum differential pulse skew
s
2.5ns maximum propagation delay
s
Low power dissipation
s
Power-Off protection
s
Fail safe protection for open-circuit, shorted and termi-
nated non-driven input conditions
s
Meets or exceeds the TIA/EIA-644 LVDS standard
s
14-Lead TSSOP package saves space
Ordering Code:
Order Number
FIN1026MTC
Package Number
MTC14
Package Description
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
R
OUT1
, R
OUT2
R
IN1+
, R
IN2+
R
IN1−
, R
IN2−
EN
EN
V
CC
GND
NC
Description
LVTTL Data Outputs
Non-Inverting LVDS Inputs
Inverting LVDS Inputs
Driver Enable Pin
Inverting Driver Enable Pin
Power Supply
Ground
No Connect
Truth Table
Inputs
EN
H
H
H
X
L or Open
EN
L or Open
L or Open
H
X
R
IN+
H
L
X
X
R
IN−
L
H
X
X
Outputs
R
OUT
H
L
H
Z
Z
L or Open Fail Safe Condition
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don’t Care
Z
=
High Impedance
Fail Safe
=
Open, Shorted, Terminated
© 2002 Fairchild Semiconductor Corporation
DS500784
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FIN1026
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
LVDS DC Input Voltage (V
IN
)
LVTTL DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
DC Output Current (I
O
)
Storage Temperature Range (T
STG
)
Max Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Machine Model)
260
°
C
10,000V
600V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to 6V
−
0.5V to 6V
16mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Magnitude of Differential Voltage
(|V
ID
|)
Common-Mode Input Voltage (V
IC
)
Input Voltage (V
IN
)
Operating Temperature (T
A
)
100mV to V
CC
0.05V to 2.35V
0 to V
CC
3.0V to 3.6V
−
65
°
C to
+
150
°
C
150
°
C
−
40
°
C to
+
85
°
C
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
V
TH
V
TL
I
IN
I
I(OFF)
V
OH
V
OL
I
OZ
V
IK
I
OS
I
CCZ
I
CC
Parameter
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Current
Power-Off Input Current
Output HIGH Voltage
Output LOW Voltage
Disabled Output Leakage Current
Input Clamp Voltage
Output Short Circuit Current
Disabled Power Supply Current
Power Supply Current
Test Conditions
See Figure 1, V
IC
= +0.05V, +1.2V,
or 2.35V
See Figure 1, V
IC
= +0.05V, +1.2V,
or 2.35V
V
IN
=
0V or V
CC
V
CC
=
0V, V
IN
=
0V or 3.6V
I
OH
= −100 µA
I
OH
= −8
mA
I
OH
=
100
µA
I
OL
=
8 mA
EN
=
0.8 and EN*
=
2V, V
OUT
=
3.6V or 0V
I
IK
= −18
mA
Receiver Enabled, V
OUT
=
0V
(one output shorted at a time)
Receiver Disabled
Receiver Enabled, (R
IN
+
=
1V and R
IN
−
=
1.4V)
or (R
IN
+
=
1.4V and R
IN
−
=
1V)
Note 2:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
Min
Typ
(Note 2)
Max
100
Units
mV
mV
µA
µA
V
−100
±20
±20
V
CC
−0.2
2.4
3.29
3.1
0
0.18
−1.5
-15
2.6
4.8
−0.8
−100
5
8.5
0.2
0.5
±20
V
µA
V
mA
mA
mA
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2
FIN1026
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLH
t
PHL
t
TLH
t
THL
t
SK(P)
t
SK(LH)
t
SK(HL)
t
SK(PP)
f
MAX
t
PZH
t
PZL
t
PHZ
t
PLZ
C
IN
C
OUT
Parameter
Propagation Delay LOW-to-HIGH
Propagation Delay HIGH-to-LOW
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Operating Frequency (Note 6)
LVTTL Output Enable Time from Z to HIGH
LVTTL Output Enable Time from Z to LOW
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
Input Capacitance
Output Capacitance
Enable Inputs
R
IN
Inputs
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
f
MAX
Criteria: Input t
R
= t
F
<
1 ns, V
ID
=
300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, V
OL
<
0.5V, V
OH
>
2.4V.
All channels switching in phase.
Test Conditions
Min
1.0
1.0
Typ
(Note 3)
Max
2.5
2.5
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
pF
pF
0.7
|V
ID
|
=
400 mV, C
L
=
10 pF
See Figure 1 and Figure 2
0.7
1.2
1.2
0.4
0.3
1.0
200
R
L
=
1kΩ, C
L
=
10 pF,
See Figure 3
375
6.0
6.0
6.0
6.0
3.0
4.2
6
Note A:
All differential input pulses have frequency
=
10MHz, t
R
or t
F
=
1ns
FIGURE 1. Differential Receiver Voltage Definitions
3
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FIN1026
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
Test Circuit for LVTTL Outputs
Voltage Waveforms Enable and Disable Times
FIGURE 3. LVTTL Outputs Test Circuit and AC Waveforms
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4
FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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