电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

FIN1018

产品描述LINE RECEIVER, PDSO8
产品类别半导体    模拟混合信号IC   
文件大小1MB,共8页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
下载文档 详细参数 选型对比 全文预览

FIN1018概述

LINE RECEIVER, PDSO8

线接收器, PDSO8

FIN1018规格参数

参数名称属性值
功能数量1
端子数量8
最小工作温度-40 Cel
最大工作温度85 Cel
加工封装描述3.10 MM, MO-187, US-8
欧盟RoHS规范Yes
状态Active
接口类型LINE RECEIVER
输入特性DIFFERENTIAL
接口标准EIA-644; TIA-644
jesd_30_codeR-PDSO-G8
jesd_609_codee3
moisture_sensitivity_level1
包装材料PLASTIC/EPOXY
ckage_codeVSSOP
包装形状RECTANGULAR
包装尺寸SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
eak_reflow_temperature__cel_260
eceive_delay_max2.5 ns
接收器位数1
seated_height_max0.9000 mm
额定供电电压3.3 V
最小供电电压3 V
最大供电电压3.6 V
表面贴装YES
温度等级INDUSTRIAL
端子涂层MATTE TIN
端子形式GULL WING
端子间距0.5000 mm
端子位置DUAL
ime_peak_reflow_temperature_max__s_30
length2.3 mm
width2 mm

文档预览

下载PDF文档
FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver
March 2001
Revised April 2002
FIN1018
3.3V LVDS 1-Bit High Speed Differential Receiver
General Description
This single receiver is designed for high speed intercon-
nects utilizing Low Voltage Differential Signaling (LVDS)
technology. The receiver translates LVDS levels, with a typ-
ical differential input threshold of 100 mV, to LVTTL signal
levels. LVDS provides low EMI at ultra low power dissipa-
tion even at high frequencies. This device is ideal for high
speed transfer of clock or data.
The FIN1018 can be paired with its companion driver, the
FIN1017, or with any other LVDS driver.
Features
s
Greater than 400Mbs data rate
s
3.3V power supply operation
s
0.4ns maximum pulse skew
s
2.5ns maximum propagation delay
s
Low power dissipation
s
Power-Off protection
s
Fail safe protection for open-circuit, shorted and termi-
nated conditions
s
Meets or exceeds the TIA/EIA-644 LVDS standard
s
Flow-through pinout simplifies PCB layout
s
8-Lead SOIC and US-8 packages save space
Ordering Code:
Order Number
FIN1018M
FIN1018MX
FIN1018K8X
Package Number
M08A
M08A
MAB08A
Package Description
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
Pin Descriptions
Pin Name
R
OUT
R
IN+
R
IN−
V
CC
GND
NC
Description
LVTTL Data Output
Non-inverting Driver Input
Inverting Driver Input
Power Supply
Ground
No Connect
Connection Diagrams
8-Lead SOIC
Function Table
Input
R
IN+
L
H
R
IN−
H
L
Outputs
R
OUT
L
H
H
Pin Assignment for US-8 Package
Fail Safe Condition
H
=
HIGH Logic Level
L
=
LOW Logic Level
Fail Safe
=
Open, Shorted, Terminated
TOP VIEW
© 2002 Fairchild Semiconductor Corporation
DS500502
www.fairchildsemi.com

FIN1018相似产品对比

FIN1018 FIN1018M
描述 LINE RECEIVER, PDSO8 LINE RECEIVER, PDSO8
功能数量 1 1
端子数量 8 8
输入特性 DIFFERENTIAL DIFFERENTIAL
接口标准 EIA-644; TIA-644 EIA-644; TIA-644
接收器位数 1 1
最小供电电压 3 V 3 V
最大供电电压 3.6 V 3.6 V
表面贴装 YES YES
温度等级 INDUSTRIAL INDUSTRIAL
端子形式 GULL WING GULL WING
端子位置 DUAL DUAL

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 637  2514  2928  2522  2547  13  51  59  52  40 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved