®
LF155-LF255-LF355
LF156-LF256-LF356
LF157-LF257-LF357
WIDE BANDWIDTH
SINGLE J-FET OPERATIONAL AMPLIFIERS
.
.
.
.
.
.
.
.
.
.
.
HIGH INPUT IMPEDANCE J-FET INPUT
STAGE
HIGH SPEED J-FET OP-AMPs : up to 20MHz,
50V/µs
OFFSET VOLTAGE ADJUSTMENT DOES NOT
DEGRADE DRIFT OR COMMON-MODE
REJECTION AS IN MOST OF MONOLITHIC
AMPLIFIERS
INTERNAL COMPENSATION AND LARGE
DIFFERENTIAL INPUT VOLTAGECAPABILITY
(UP TO V
CC+
)
N
DIP8
(Plastic Package)
D
SO8
(Plastic Micropackage)
TYPICAL APPLICATIONS
PRECISION HIGH SPEED INTEGRATORS
FAST D/A AND CONVERTERS
HIGH IMPEDANCE BUFFERS
WIDEBAND, LOW NOISE, LOW DRIFT
AMPLIFIERS
LOGARITHIMIC AMPLIFIERS
PHOTOCELL AMPLIFIERS
SAMPLE AND HOLD CIRCUITS
ORDER CODES
Part Number
LF355, LF356, LF357
LF255, LF256, LF257
LF155, LF156, LF157
Example :
LF355N
Temperature
Range
0
o
C, +70
o
C
–40 C, +105 C
–55 C, +125 C
o
o
o
o
Package
N
•
•
•
D
•
•
•
PIN CONNECTIONS
(top view)
1
DESCRIPTION
These circuits are monolithic J-FET input operational
amplifiers incorporating well matched, high voltage
J-FET on the same chip with standard bipolar transis-
tors.
This amplifiers feature low input bias and offset cur-
rents, low input offset voltage and input offset voltage
drift,coupledwith offsetadjust which doesnot degrade
drift or common-mode rejection.
The devices are also designed for high slew rate, wide
bandwidth,extremelyfastsettlingtime, lowvoltageand
current noise and a low 1/f noise level.
July 1998
8
7
6
5
1
2
3
4
- Offset Null 1
- Inverting input
- Non-inverting input
- V
CC-
5
6
7
8
-
-
-
-
Offset Null 2
Output
+
V
CC
N.C.
2
3
4
1/14
LF155 - LF156 - LF157
SCHEMATIC DIAGRAM
V
i o
ADJUSTMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
i
V
id
P
tot
T
oper
Supply Voltage
Input Voltage - (note 1)
Differential Input Voltage
Power Dissipation
Output Short-circuit Duration
Operating Free Air Temperature Range
LF155-LF156-LF157
LF255-LF256-LF257
LF355-LF356-LF357
Parameter
Value
±22
±20
±40
570
Infinite
-55 to +125
–40 to +105
0 to 70
–65 to 150
o
Unit
V
V
V
mW
C
T
stg
Storage Temperature Range
o
C
2/14
LF155 - LF156 - LF157
ELECTRICAL CHARACTERISTICS
LF155, LF156, LF157
-55
o
C
≤
T
amb
≤
+125
o
C
LF255, LF256, LF257
-40
o
C
≤
T
amb
≤
+105
o
C
(unless otherwise specified)
Symbol
V
io
Parameter
Input Offset Voltage (R
S
= 50Ω)
T
amb
= 25
o
C
T
min.
≤
T
amb
≤
T
max.
Input Offset Current - (note 3)
o
T
amb
= 25 C
T
min.
≤
T
amb
≤
T
max.
Input Bias Current - (note 3)
T
amb
= 25
o
C
T
min.
≤
T
amb
≤
T
max.
±5V ≤
V
CC
≤ ±20V
±5V ≤
V
CC
≤ ±20V
LF155 - LF156 - LF157
LF255 - LF256 - LF257
Min.
Typ.
Max.
3
5
7
6.2
20
20
1
100
50
5
pA
nA
nA
pA
nA
nA
V/mV
Unit
mV
LF155, LF156, LF157
LF255, LF256, LF257
3
LF155, LF156, LF157
LF255, LF256, LF257
20
I
io
I
ib
A
vd
SVR
I
CC
DV
io
DV
io
/V
io
V
icm
CMR
±V
OPP
GBP
LF155, LF156, LF157
LF255, LF256, LF257
Large Signal Voltage Gain (R
L
= 2kΩ, V
O
=
±10V,
V
CC
=
±15V)
o
T
amb
= 25 C
T
min.
≤
T
amb
≤
T
max.
Supply Voltage Rejection Ratio - (note 4)
Supply Current (V
CC
=
±15V,
no load)
LF155, LF255
T
amb
= 25
o
C
LF156, LF256
LF157, LF257
Input Offset Voltage Drift (R
S
= 50Ω)
Change in Average Temperature Coefficient with V
io
adjust
(R
S
= 50Ω) - (note 2)
Input Common Mode Voltage Range (V
CC
=
±15V,
T
amb
= 25
o
C)
Common Mode Rejection Ratio
Output Voltage Swing (V
CC
=
±15V)
R
L
= 10kΩ
R
L
= 2kΩ
Gain Bandwidth Product (V
CC
=
±15V,
T
amb
= 25
o
C)
LF155, LF255
LF156, LF256
LF157, LF257
o
Slew Rate (V
CC
=
±15V,
T
amb
= 25 C)
LF155, LF255
A
V
= 1
LF156, LF256
LF157, LF257
A
V
= 5
o
Input Resistance (T
amb
= 25 C)
Input Capacitance (V
CC
=
±15V,
T
amb
= 25
o
C)
Equivalent Input Noise Voltage
(V
CC
=
±15V,
T
amb
= 25
o
C, R
S
= 100Ω)
f = 1000Hz
LF155, LF255
LF156, LF256
LF157, LF257
f = 100Hz
LF155, LF255
LF156, LF256
LF157, LF257
Equivalent Input Noise Current
(V
CC
=
±15V,
T
amb
= 25
o
C, f = 100Hz or f = 1000Hz)
Settling Time (V
CC
=
±15V,
T
amb
= 25
o
C) - (note 5)
LF155, LF255
LF156, LF256
LF157, LF257
50
25
85
200
100
2
5
5
5
0.5
4
7
7
µV/
C
o
µV/
C
V
dB
V
o
dB
mA
±11
85
±12
±10
+15.1
-12
100
±13
±12
2.5
5
20
MHz
SR
V/µs
7.5
30
5
12
50
10
12
3
R
i
C
i
e
n
20
12
12
25
15
15
0.01
4
1.5
1.5
Ω
pF
nV
Hz
√
i
n
t
s
pA
Hz
√
µs
3/14
LF155 - LF156 - LF157
ELECTRICAL CHARACTERISTICS
LF355, LF356, LF357
0
o
C
≤
T
amb
≤
+70
o
C
Symbol
V
io
I
io
I
ib
A
vd
SVR
I
CC
DV
io
DV
io
/V
io
V
icm
CMR
±V
OPP
GBP
Parameter
Input Offset Voltage (R
S
= 50Ω)
T
amb
= 25
o
C
T
min.
≤
T
amb
≤
T
max.
Input Offset Current - (note 3)
o
T
amb
= 25 C
T
min.
≤
T
amb
≤
T
max.
Input Bias Current - (note 3)
o
T
amb
= 25 C
T
min.
≤
T
amb
≤
T
max.
Large Signal Voltage Gain (R
L
= 2kΩ, V
O
=
±10V)
o
T
amb
= 25 C
T
min.
≤
T
amb
≤
T
max.
Supply Voltage Rejection Ratio - (note 4)
Supply Current (no load)
o
LF355
T
amb
= 25 C
LF356, LF357
Input Offset Voltage Drift (R
S
= 50Ω) - (note 2)
Change in Average Temperature Coefficient with V
io
adjust
(R
S
= 50Ω)
Input Common Mode Voltage Range (T
amb
= 25
o
C)
Common Mode Rejection Ratio
Output Voltage Swing
Gain Bandwidth Product T
amb
= 25 C)
o
o
V
CC
=
±15V
, (unless otherwise specified)
LF355 - LF356 - LF357
Min.
Typ.
Max.
3
10
13
50
2
200
8
pA
nA
pA
nA
V/mV
Unit
mV
3
20
25
15
80
200
100
2
5
5
0.5
4
10
µV/
o
C
o
µV/
C
per mV
V
dB
V
MHz
dB
mA
±10
80
±12
±10
R
L
= 10kΩ
R
L
= 2kΩ
LF355
LF356
LF357
LF355
LF356
LF357
+15.1
-12
100
±13
±12
2.5
5
20
5
12
50
12
10
3
20
12
25
15
0.01
4
1.5
SR
Slew Rate (T
amb
= 25 C)
A
V
= 1
V/µs
R
i
C
i
e
n
i
n
t
s
A
V
= 5
o
Input Resistance (T
amb
= 25 C)
o
Input Capacitance (Tamb = 25 C)
Equivalent Input Noise Voltage (T
amb
= 25
o
C, R
S
= 100Ω)
f = 1000Hz
LF355
LF356, LF357
f = 100Hz
LF355
LF356, LF357
Equivalent Input Noise Current
o
(T
amb
= 25 C, f = 100Hz or f = 1000Hz)
Settling Time (T
amb
= 25
o
C) - (note 5)
LF355
LF356, LF357
Ω
pF
nV
Hz
√
pA
Hz
√
µs
Notes :
1. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
2. The temperature coefficient of the adjusted input offset voltage changes only a small amount (0.5µV/
o
C typically) for each mV
of adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are alsounaffected by
offset adjustment.
3. The input bias currents are junction leakage currents which approximately double for every 10
o
C increase in the junction
temperature T
amb
. Due to limited production test time, the input bias current measured is correlated to junction temperature.
In a normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation,
P
tot
-T
amb
=T
amb
+R
th(j-a)
xP
tot
where Rt
h(j-a)
is the thermal resistance from junction to ambient. Use of a heatsink is recommended
f input currents are to be kept to a minimum.
4. Supply voltage rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with
common practise.
5. Settling time is defined here, for a unity gain inverter connection using 2kΩ resistors for the LF155, LF156 series. It is the time
required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from
the time a 10V step input is applied to the inverter. For the LF157 series A
V
= -5, the feedback resistor from output to input is 2kΩ
and the output step is 10V.
4/14
LF155 - LF156 - LF157
APPLICATION HINTS
The LF155, LF156, LF157 series are op amps with J-
FETinput transistors. TheseJFETs havelarge reverse
breakdown voltagesfromgatetosource or drain elimi-
natingtheneed of clamps across the inputs.Therefore
large differential input voltages can easily be accom-
modatedwithoutalarge increaseof inputcurrents. The
maximum differential input voltage is independent of
the supply voltage. However, neitherof thenegativein-
put voltagesshouldbe allowed to exceedthe negative
supply as this will cause large currents to flow which
can result in a destroyed unit. Exceeding the negative
common-modelimit on either inputwill causeareversal
of thephasetotheoutputandforce the amplifier output
to the correspondinghigh or lowstate. Exceedingthe
negativecommon-mode limit on bothinputs will force
the amplifier outputto a highstate.In neithercasedoes
a latch occur since raising the input back within the
common-mode range again puts the input stage and
thustheamplifierin a normal operatingmode. Exceed-
ingthepositive common-modelimit on asingle input will
not changethephase of the output however, if bothin-
putsexceedthe limit, theoutput of theamplifier will be
forcedto ahighstate.Theseamplifiers will operatewith
the common-mode input voltage equal to the positive
supply. In fact, the common-modevoltagecanex-
ceedthepositivesupplyby approximately 100mV inde-
pendentof supply volt-age and over thefull operat-
ingtemperaturerange.The positive suplly can there-
forebe used as a referenceonaninput as, forexample,
in a supply current monitor and/orlimiter. Precautions-
shouldbe taken to ensurethat thepowersupply forthe
integrated circuit never becomes re-versed in polarity
or that the unit is not inadvertentlyin-stalledbackwards
in a socket as an unilimited current surge throughthe
resulting forward diode within the IC couldcausefusin-
goftheinternalconductorsandresultin a destroyedunit.
Because these amplifiers are JFET rather than MOS-
FET input op amps they do not require special han-
dling.
Allof thebiascurrentsintheseamplifiersareset by FET
current sources. The drain currents for the amplifiers
are therefore essentially independent of supply volt-
ages.
As with most amplifiers, care should betakenwith lead
dress, components placement and supply decoupling
in order to ensure stability. For example, resistors from
the output to an input should be placed with the body
close to theinput to minimiz ”pickup”and maximize the
frequency of the feedback pole by minimizing the ca-
pacitancefromthe input to ground.
A feedback pole is createdwhen the feedbackaround
any amplifier is resistive. The parallel resistance and
capacitancefromthe input of thedevice(usually the in-
vertinginput)toacgroundsetthefrequencyofthepole.In
many instances the frequency of this pole is much
greaterthanthe expected3 dBfrequencyof the closed
loopgain and consequentlythereisnegligible effect on
stability margin. However, if the feedback pole is less
than approximately six time the expected 3 dB fre-
quencyaleadcapacitor should be placed from the out-
put to the input of the op amp. The value of that added
capacitor should be such that the RC time constant of
this capacitor and the resistance it parallels is greater
than or equal to the original feedback pole time con-
stant.
5/14
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
