CMT08N50
P
OWER
F
IELD
E
FFECT
T
RANSISTOR
GENERAL DESCRIPTION
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage-blocking capability
without degrading performance over time. In addition, this
advanced MOSFET is designed to withstand high energy in
avalanche and commutation modes. The new energy
efficient design also offers a drain-to-source diode with a
fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, converters and
PWM motor controls, these devices are particularly well
suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer
additional and safety margin against unexpected voltage
transients.
FEATURES
Robust High Voltage Termination
Avalanche Energy Specified
Source-to-Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
I
DSS
and V
DS
(on) Specified at Elevated Temperature
PIN CONFIGURATION
TO-220/TO-220FP
SYMBOL
D
Top View
GATE
SOURCE
DRAIN
G
S
1
2
3
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
Rating
Drain to Current
－
Continuous
－
Pulsed
Gate-to-Source Voltage
－
Continue
－
Non-repetitive
Total Power Dissipation
TO-220
TO-220FP
Operating and Storage Temperature Range
Single Pulse Drain-to-Source Avalanche Energy
－
T
J
= 25℃
(V
DD
= 100V, V
GS
= 10V, I
L
= 8A, L = 10mH, R
G
= 25Ω)
Thermal Resistance
－
Junction to Case
－
Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8” from case for 10 seconds
θ
JC
θ
JA
T
L
1.0
62.5
260
℃
℃/W
T
J
, T
STG
E
AS
Symbol
I
D
I
DM
V
GS
V
GSM
P
D
125
40
-55 to 150
320
℃
mJ
Value
8.0
32
±20
±40
V
V
W
Unit
A
2003/03/31
Preliminary
Rev. 1.0
Champion Microelectronic Corporation
Page 1
CMT08N50
P
OWER
F
IELD
E
FFECT
T
RANSISTOR
ORDERING INFORMATION
Part Number
CMT08N50N220
CMT08N50N220FP
Package
TO-220
TO-220 Full Package
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, T
J
= 25℃.
CMT08N50
Characteristic
Drain-Source Breakdown Voltage
(V
GS
= 0 V, I
D
= 250
μA)
Drain-Source Leakage Current
(V
DS
= 500 V, V
GS
= 0 V)
(V
DS
= 400 V, V
GS
= 0 V, T
J
= 125℃)
Gate-Source Leakage Current-Forward
(V
gsf
= 20 V, V
DS
= 0 V)
Gate-Source Leakage Current-Reverse
(V
gsr
= 20 V, V
DS
= 0 V)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
μA)
Static Drain-Source On-Resistance (V
GS
= 10 V, I
D
= 4.0A) *
Drain-Source On-Voltage (V
GS
= 10 V)
(I
D
= 8.0 A)
Forward Transconductance (V
DS
= 50 V, I
D
= 4.0A) *
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Internal Drain Inductance
(Measured from the drain lead 0.25” from package to center of die)
Internal Drain Inductance
(Measured from the source lead 0.25” from package to source bond pad)
SOURCE-DRAIN DIODE CHARACTERISTICS
Forward On-Voltage(1)
Forward Turn-On Time
Reverse Recovery Time
(I
S
= 8.0 A, V
GS
= 0 V,
d
IS
/d
t
= 100A/µs)
V
SD
t
on
t
rr
**
320
1.5
V
ns
ns
L
S
7.5
nH
(V
DS
= 400 V, I
D
= 8.0 A,
V
GS
= 10 V)*
(R
Go
+ C17n = 9.1Ω) *
(V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
L
D
4.9
1450
190
45.4
15
33
40
32
40
8.0
17
4.5
1680
246
144
50
72
150
60
64
mmhos
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
nH
R
DS(on)
V
DS(on)
5.0
0.8
7.2
Ω
V
V
GS(th)
2.0
4.0
V
I
GSSR
100
nA
I
GSSF
I
DSS
25
250
100
nA
μA
Symbol
V
(BR)DSS
Min
500
Typ
Max
Units
V
* Pulse Test: Pulse Width
≦300µs,
Duty Cycle
≦2%
** Negligible, Dominated by circuit inductance
2003/03/31
Preliminary
Rev. 1.0
Champion Microelectronic Corporation
Page 2
FPGA/CPLD
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