SPP2305
P-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPP2305 is the P-Channel logic enhancement mode
power field effect transistors are produced using high cell
density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery powered
circuits, and low in-line power loss are needed in a very
small outline surface mount package.
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
FEATURES
-15V/-3.5A,R
DS(ON)
= 70mΩ@V
GS
=-4.5V
-15V/-3.0A,R
DS(ON)
= 85mΩ@V
GS
=-2.5V
-15V/-2.0A,R
DS(ON)
=105mΩ@V
GS
=-1.8V
Super high density cell design for extremely low
R
DS (ON)
Exceptional on-resistance and maximum DC
current capability
SOT-23-3L package design
PIN CONFIGURATION(SOT-23-3L)
PART MARKING
2007/03/30
Ver.1
Page 1
SPP2305
P-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
ORDERING INFORMATION
Part Number
SPP2305S23RG
※
Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※
SPP2305S23RG : Tape Reel ; Pb – Free
Package
SOT-23-3L
Part
Marking
05YW
Symbol
G
S
D
Description
Gate
Source
Drain
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
S
P
D
T
J
T
STG
R
θJA
Typical
-15
±12
-3.5
-2.8
-10
-1.6
1.25
0.8
150
-55/150
120
Unit
V
V
A
A
A
W
℃
℃
℃
/W
2007/03/30
Ver.1
Page 2
SPP2305
P-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=-250uA
V
GS(th)
V
DS
=V
GS
,I
D
=-250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
V
DS
=0V,V
GS
=±10V
V
DS
=-12V,V
GS
=0V
V
DS
=-12V,V
GS
=0V
T
J
=55℃
V
DS
≦-5V,V
GS
=-4.5V
V
DS
≦-5V,V
GS
=-2.5V
V
GS
=-4.5V,I
D
=-3.5A
V
GS
=-2.5V,I
D
=-3.0A
V
GS
=-1.8V,I
D
=-2.0A
V
DS
=-5V,I
D
=-3.5A
I
S
=-1.5A,V
GS
=0V
-15
-0.35
-0.85
±100
-1
-10
-4
-2
0.055
0.065
0.085
8.5
-0.8
0.70
0.85
0.105
-1.2
V
nA
uA
A
Ω
S
V
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DS
=-6V,V
GS
=-4.5V
I
D
≡-2.8A
V
DS
=-6V,V
GS
=0V
f=1MHz
4.8
1.0
1.0
485
85
40
10
8
nC
pF
16
23
25
20
ns
V
DD
=-6V,R
L
=6Ω
I
D
≡-1.0A,V
GEN
=-4.5V
R
G
=6Ω
13
18
15
2007/03/30
Ver.1
Page 3
FPGA/CPLD
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