SPN6561
Dual N-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPN6561 is the Dual N-Channel enhancement mode
power field effect transistors are produced using high cell
density , DMOS trench technology. This high density
process is especially tailored to minimize on-state
resistance and provide superior switching performance.
These devices are particularly suited for low voltage
applications such as notebook computer power
management and other battery powered circuits where
high-side switching , low in-line power loss, and
resistance to transients are needed.
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
FEATURES
N-Channel
30V/2.8A,R
DS(ON)
= 60mΩ@V
GS
=10V
30V/2.3A,R
DS(ON)
= 80mΩ@V
GS
=4.5V
Super high density cell design for extremely low
RDS (ON)
Exceptional on-resistance and maximum DC
current capability
SOT-23-6L package design
PIN CONFIGURATION( SOT-23-6L )
PART MARKING
2006/06/05
Ver.1
Page 1
SPN6561
Dual N-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
4
5
6
Symbol
G1
S2
G2
D2
S1
D1
Description
Gate 1
Source 2
Gate 2
Drain 2
Source 1
Drain1
ORDERING INFORMATION
Part Number
SPN6561S26RG
※
Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※
SPN6561S26RG : Tape Reel ; Pb – Free
Package
SOT-23-6L
Part
Marking
61YW
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
≤
10sec
Steady State
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
S
P
D
T
J
T
STG
R
θJA
Typical
30
±20
2.8
2.3
10
1.25
1.15
0.75
Unit
V
V
A
A
A
W
℃
℃
-55/150
-55/150
50
90
℃/W
2006/06/05
Ver.1
Page 2
SPN6561
Dual N-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=250uA
V
GS(th)
V
DS
=V
GS
,I
D
=250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
V
DS
=0V,V
GS
=±20V
V
DS
=30V,V
GS
=1.0V
V
DS
=30V,V
GS
=0.0V
T
J
=55℃
V
DS
≧4.5V,V
GS
=10V
V
DS
≧4.5V,V
GS
=4.5V
V
GS
= 10V,I
D
=2.8A
V
GS
=4.5V,I
D
=2.1A
V
DS
=4.5V,I
D
=2.5A
I
S
=1.25A,V
GS
=0V
30
1.0
3.0
±100
1
10
6
4
0.043
0.056
4.6
0.8
0.060
0.080
1.2
V
nA
uA
A
Ω
S
V
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DS
=15V
GS
=10V
I
D
≡2.5
4.5
0.8
1.0
240
110
17
8
10
nC
V
DS
=15V
GS
=0V
f=1MHz
pF
20
30
35
20
ns
V
DD
=15R
L
=15
I
D
≡1.0A,V
GEN
=10
R
G
=6Ω
12
17
8
2006/06/05
Ver.1
Page 3
嵌入式系统
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