SPN1423A
N-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPN1423A is the N-Channel logic enhancement
mode power field effect transistors are produced using
high cell density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery powered
circuits where high-side switching , and low in-line
power loss are needed in a very small outline surface
mount package.
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
FEATURES
20V/4.0A,R
DS(ON)
=80mΩ@V
GS
=4.5V
20V/3.4A,R
DS(ON)
=90mΩ@V
GS
=2.5V
20V/2.8A,R
DS(ON)
=110mΩ@V
GS
=1.8V
Super high density cell design for extremely low
RDS (ON)
Exceptional on-resistance and maximum DC
current capability
SOT-353 ( SC – 70 ) package design
PIN CONFIGURATION ( SOT-353 ; SC-70 )
PART MARKING
2008/02/20
Ver.4
Page 1
SPN1423A
N-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
2
3
1,4,5
Symbol
G
S
D
Description
Gate
Source
Drain
ORDERING INFORMATION
Part Number
SPN1423AS35RG
※
Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※
SPN1423AS35RG : Tape Reel ; Pb – Free
Package
SOT-353
Part
Marking
2AYW
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
S
P
D
T
J
T
STG
R
θJA
Typical
20
±12
Unit
V
V
A
A
A
W
℃
℃
℃/W
2.4
1.7
6
1.6
0.95
0..51
-55/150
-55/150
105
2008/02/20
Ver.4
Page 2
SPN1423A
N-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=250uA
V
GS(th)
V
DS
=V
GS
,I
D
=250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DD
=6V,R
L
=6Ω
I
D
≡1.0A,V
GEN
=4.5V
R
G
=6Ω
V
DS
=6V,V
GS
=0V
f=1MHz
V
DS
=0V,V
GS
=±12V
V
DS
=20V,V
GS
=0V
V
DS
=20V,V
GS
=0V
T
J
=55℃
V
DS
≦5V,V
GS
=4.5V
V
GS
=4.5V,I
D
=4.0A
V
GS
=2.5V,I
D
=3.4A
V
GS
=1.8V,I
D
=2.8A
V
DS
=5V,I
D
=-3.6A
I
S
=1.6A,V
GS
=0V
20
0.4
1.0
±100
1
5
6
0.065
0.075
0.090
10
0.8
4.8
1.0
1.0
485
85
40
8
12
30
12
14
18
35
16
0.080
0.090
0.110
1.2
8
V
nA
uA
A
Ω
S
V
V
DS
=6V,V
GS
=4.5V
I
D
≡2.8A
nC
pF
ns
2008/02/20
Ver.4
Page 3