SPN1423
N-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPN1423 is the N-Channel logic enhancement mode
power field effect transistors are produced using high cell
density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery powered
circuits where high-side switching , and low in-line
power loss are needed in a very small outline surface
mount package.
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
FEATURES
20V/2.8A,R
DS(ON)
= 90mΩ@V
GS
=4.5V
20V/2.2A,R
DS(ON)
= 100mΩ@V
GS
=2.5V
Super high density cell design for extremely low
R
DS (ON)
Exceptional on-resistance and maximum DC
current capability
SOT-323 ( SC–70 ) package design
PIN CONFIGURATION ( SOT-323 ; SC-70 )
PART MARKING
2005/05/25
Ver.1
Page 1
SPN1423
N-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
Symbol
G
S
D
Description
Gate
Source
Drain
ORDERING INFORMATION
Part Number
SPN1423S32RG
※
Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※
SPN1423S32RG : Tape Reel ; Pb – Free
Package
SOT-323
Part
Marking
23YW
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
S
P
D
T
J
T
STG
R
θJA
Typical
20
±12
2.8
2.2
10
1.6
0.33
Unit
V
V
A
A
A
W
℃
℃
℃/W
0.21
150
-55/150
100
2005/05/25
Ver.1
Page 2
SPN1423
N-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=250uA
V
GS(th)
V
DS
=V
GS
,I
D
=250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
V
DS
=0V,V
GS
=±12V
V
DS
=20V,V
GS
=0V
V
DS
=20V,V
GS
=0V
T
J
=55℃
V
DS
≧5V,V
GS
=4.5V
V
DS
≧5V,V
GS
=2.5V
V
GS
=4.5V,I
D
=2.8A
V
GS
=2.5V,I
D
=2.2A
V
DS
=5V,I
D
=2.8A
I
S
=1.6A,V
GS
=0V
20
0.45
1.2
±100
1
10
5
4
0.055
0.075
10
0.85
0.090
0.100
1.2
V
nA
uA
A
Ω
S
V
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DS
=10V,V
GS
=4.5V
I
D
≡2.8A
5.4
0.65
1.4
340
115
33
12
10
nC
V
DS
=10V,V
GS
=0V
f=1MHz
pF
25
60
60
25
ns
V
DD
=10V,R
L
=5.5Ω
I
D
≡2.8A,V
GEN
=4.5V
R
G
=6Ω
36
34
10
2005/05/25
Ver.1
Page 3
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