Silan
Semiconductors
DTMF RECEIVER
DESCRIPTION
The SC9270C/D is a complete DTMF receiver integrating both
the bandsplit filter and digital decoder functions. The filter section
uses switched capacitor techniques for high- and low-group filters
and dial-tone rejection. Digital counting techniques are employed in
the decoder to detect and decode all 16 DTMF tone-pairs into a 4-bit
code. External component count is minimized by on-chip provision of
a differential input amplifier, clock-oscillator and latched 3-state bus
interface.
SC9270C/D
FEATURES
*Complete receiver in an 18-pin package
*Excellent performance
*CMOS, single 5 volt operation,
*Widely operating voltage: 1.2V ~ 5.25V
*Minimum board area
*Central office quality
*Low power consumption
*Power-Down mode (SC9270D only)
*Inhibit-mode (SC9270D only)
DIP-18
APPLICATIONS
*Paging systems
*Repeater systems / Mobile radio
*Credit card systems
*Remote control
*Personal computers
PIN CONFIGURATIONS
IN+
IN-
GS
VREF
IC*
IC*
OSCI
OSCO
VSS
1
2
3
SC9270C
4
5
6
7
8
9
18
VDD
17
St/GT
16
ESt
15
StD
14
Q4
13
Q3
12
Q2
11
Q1
10
TOE
IN+
IN-
GS
VREF
INH
PWDN
OSCI
OSCO
VSS
1
2
3
4
5
6
7
8
9
SC9270D
18
VDD
17
St/GT
16
ESt
15
StD
14
Q4
13
Q3
12
Q2
11
Q1
10
TOE
* Connect to V
SS
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Rev: 1.1
2001.04.27
1
Silan
Semiconductors
BLOCK DIAGRAM
V
DD
V
SS
PWDN
V
REF
INH
SC9270C/D
4
-
+
18
9
6
5
BIAS
CIRCUIT
11
Q1
Chip ref
Chip power
IN+
1
IN-
2
GS
+
-
Chip bias
DIAL
TONE
FILTER
HIGH GROUP
FILTER
Zero crossing detectors
CODE
DIGITAL
CONVERTER
DETECTION
AND
ALGORITHM
LATCH
12
Q2
13
Q3
14
Q4
3
HIGH GROUP
FILTER
Chip clock
St
GT
STEERING
LOGIC
7
OSCI
8
OSCO
17
St/GT
16
ESt
15
StD
10
TOE
Figure 1. block diagram
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2, 3)
Characteristic
Power Supply Voltage
Voltage on any pin
Current at any pin
Operating temperature
Storage Temperature
Package power dissipation
Symbol
V
DD
-V
SS
--
--
Topr
Tstg
Value
6
V
SS
-0.3 ~ V
DD
+0.3
10
-40~+85
-65~+150
500
Unit
V
V
mA
°C
°C
mW
Note: 1. Absolute maximum ratings are those values beyond which damage to the device may occur.
2. Unless otherwise specified, all voltages are referenced to ground.
3. Power dissipation temperature derating: -12 mV / from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
(Note 1)
Parameter
Positive Supply Voltages
Oscillator Clock Frequency
Oscillator Frequency Tolerance
Symbol
V
DD
fc
∆fc
--
--
Conditions
V
SS
=0V
Min
1.2
--
--
Typ
(Note 2)
5
3.579545
±0.1
Max
--
--
--
Unit
V
MHz
%
Note: 1. Voltages are with respect to ground(Vss), unless otherwise stated.
2 .Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Rev: 1.1
2001.04.27
2
Silan
Semiconductors
DC ELECTRICAL CHARACTERISTICS
Parameter
SUPPLY
Operating Supply Voltage
Operating Supply Current
Power Consumption
Standby Current
V
DD
I
CC
P
O
I
S
V
IL
V
IH
I
IH
/I
IL
I
SO
R
IN
V
TSt
V
OL
V
OH
I
OL
I
OH
V
REF
R
OR
--
--
f=3.579MHz; V
DD
=5V
PWDN pin = V
DD
--
--
V
IN
= V
SS
or V
DD
TOE(Pin 10)=0V
@1kHz
--
No load
No load
V
OUT
=0.4V
V
OUT
=4.6V
No load
--
SC9270C/D
Symbol
Conditions
Min
1.2
--
--
--
--
3.5
--
--
--
--
--
--
1.0
0.4
2.4
--
Typ
--
3.0
15
--
--
--
0.1
7.5
10
2.35
0.03
4.97
2.5
0.8
--
10
Max
5.25
7.0
35
100
1.5
--
--
15
--
--
--
--
--
--
2.7
--
Unit
V
mA
mW
µA
V
V
µA
µA
MΩ
V
V
µA
mA
mA
V
kΩ
INPUTS
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
Pull up(Source) Current
Input Impedance (IN+, IN-)
Steering Threshold Voltage
OUTPUTS
Low Level Output Voltage
High Level Output Voltage
Output Low(Sink) Current
Output High(Source) Current
V
REF
Output Voltage
V
REF
Output Resistance
OPERATING CHARACTERISTICS
Gain Setting Amplifier
Parameter
Input Leakage Current
Input Resistance
Input Offset Voltage
Power Supply Rejection
Common Mode Rejection
DC Open Loop Voltage Gain
Open Loop Unity Gain Bandwidth
Output Voltage Swing
Tolerable capacitive load(GS)
Tolerable resistive load(GS)
Common Mode Range
Symbol
I
IN
R
IN
V
OS
PSRR
CMRR
A
VOL
f
C
V
O
C
L
R
L
V
CM
Conditions
V
SS
< V
IN
< V
DD
--
--
1kHz
-3.0V < V
IN
< 3.0V
--
--
R
L
≥100kΩ
to V
SS
--
--
No load
Min
--
--
--
--
--
--
--
--
--
--
--
Typ
±100
10
±25
60
60
65
1.5
4.5
100
50
3.0
Max
--
--
--
--
--
--
--
--
--
--
--
Unit
nA
MΩ
mV
dB
dB
dB
MHz
V
PP
PF
kΩ
V
PP
Notes : 1. All voltages referenced to V
DD
unless otherwise noted.
2. V
DD
= 5.0V, V
SS
= 0V, T
A
= 25°C .
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Rev: 1.1
2001.04.27
3
Silan
Semiconductors
SC9270C/D
AC CHARACTERISTICS
(All voltage referenced to Vss otherwise noted; V
DD
=5.0V, V
SS
=0V, T
A
=25°C,
f
CLK
=3.579545 MHz, using test circuit of figure 2 & 3. Typical figures are at 25°C and are for design aid only: not
guaranteed and not subject to production testing)
Parameter
SIGNAL CONDITIONS
Symbo
l
--
Test Conditions
Min
Typ
Max
Unit
Note:1,2,3,5,6,9,11
Note:1,2,3,5,6,9,11
Note:1,2,3,5,6,9,11
Note:1,2,3,5,6,9,11
Note:2,3,6,9,11
Note:2,3,6,9,11
Note:2,3,5,9,11
Note:2,3,5,11
Note:2,3,4,5,9,13
Note:2,3,4,5,7,9,10
Note:2,3,4,5,8,9,11
Refer to Fig. 4. Note:12
Refer to Fig. 4. Note:12
User adjustable
User adjustable
User adjustable
User adjustable
TOE=V
DD
--
--
+1
883
--
--
--
±3.5
-18.5
--
--
5
0.5
--
20
--
20
--
--
--
--
--
3.5759
--
--
40
--
--
--
--
--
10
10
±1.5%±2Hz
-40
7.75
--
--
--
--
--
--
--
dBm
mV
RMS
dBm
mV
RMS
dB
dB
Valid Input Signal Levels
(each tone of composite signal)
--
--
--
--
--
--
--
--
--
--
t
DP
t
DA
t
REC
t
REC
t
ID
t
DO
t
PQ
Positive Twist Accept
Negative Twist Accept
Frequency Deviation Accept Limit
Frequency Deviation Reject Limit
Thrid Tone Tolerance
Noise Tolerance
Dial Tone Tolerance
--
-12
+18
14
4
--
--
--
--
8
12
4.5
50
300
3.5759
--
--
50
--
dB
dB
dB
ms
ms
ms
ms
ms
ms
µs
µs
µs
ns
ns
MHz
ns
ns
%
pf
--
16
8.5
40
--
40
--
11
--
--
--
--
3.581
110
110
60
30
TIMING
Tone Present Detection Time
Tone Absent Detection Time
Tone Duration Accept
Tone Duration Reject
Interdigit Pause Accept
Interdigit Pause Reject
OUTPUTS
Propagation Delay (St to Q)
Propagation Delay (St to StD)
Output Data Set Up (Q to Std)
Propagation Delay (TOE to Q Enable)
Propagation Delay (TOE to Q Disable)
t
PSED
TOE=V
DD
t
QSED
TOE=V
DD
t
PTE
t
PTD
f
C
R
L
=10kΩ, C
L
=50pf
R
L
=10kΩ, C
L
=50pf
--
CLOCK
Crystal/Clock Frequency
Clock Input Rise Time
Clock Input Fall Time
Clock Input Duty Time
Capacitive Load (OSCO)
t
LHCL
Ext. clock
t
HLCL
Ext. clock
DC
CL
Ext. clock
C
LO
--
Notes: 1. dBm = decibels above or below a reference power of 1mW into a 600 Ohm load.
2. Digit sequences consists of all 16 DTMF tones.
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Rev: 1.1
2001.04.27
4
Silan
Semiconductors
3. Tone duration = 40mS Tone pause = 40mS.
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have an equal amplitude.
6. Tone pair is deviated by ±1.5% ±2Hz.
7. Bandwidth limited (3kHz) Gaussian Noise.
8. The precise dial tone frequencies are (350Hz and 440Hz) ±2%.
9. For an error rate of less than 1 in 10,000.
10. Referenced to the lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept.
12. For guard time calculation purpose.
SC9270C/D
13. Referenced to Fig.10 Input DTMF Tone level at –25dBm(-28dBm at GS Pin) interference Frequency
Range between 480—3400Hz.
5V
SC9270C
1
IN+
IN-
GS
V
REF
IC
IC
OSCI
OSCO
V
SS
V
DD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
0.1µf
100nf
5V
SC9270D
1
IN+
IN-
GS
V
REF
INH
PWDN
OSCI
OSCO
V
SS
V
DD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
0.1µf
100nf
18
17
16
15
14
13
12
11
10
3.58MHz
300k
100nf
100k
100k
18
17
16
15
14
13
12
11
10
300k
2
3
4
5
6
3.58MHz
100nf
Vin
100k
100k
5V
2
3
4
5
6
7
8
9
7
8
9
Figure 2. Single ended input cofiguration
Figure 3. Single ended input cofiguration
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Rev: 1.1
2001.04.27
5
stm32/stm8
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