ESMT
Flash
F25L32QA (2S)
32 Mbit Serial Flash Memory
with Dual and Quad
FEATURES
Single supply voltage 2.65~3.6V
Standard, Dual and Quad SPI
Speed
- Read max frequency: 50MHz
- Fast Read max frequency: 50MHz / 86MHz / 104MHz
- Fast Read Dual/Quad max frequency: 50MHz / 86MHz /
104MHz
(100MHz / 172MHz / 208MHz equivalent Dual SPI;
200MHz / 344MHz / 416MHz equivalent Quad SPI)
Low power consumption
- Active current: 25 mA (max.)
- Standby current: 30
μ
A (max.)
- Deep Power Down current: 10
μ
A (max.)
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Page programming time: 1.5 ms (typical)
Erase
- Chip Erase time 10 sec (typical)
- 64K bytes Block Erase time 1 sec (typical)
- 32K bytes Block Erase time 500 ms (typical)
- 4K bytes Sector Erase time 120 ms (typical)
Page Programming
- 256 byte per programmable page
Program / Erase Suspend
Lockable 512 bytes OTP security sector
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
End of program or erase detection
Write Protect (
WP
)
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25L32QA –50PG2S
F25L32QA –86PG2S
F25L32QA –100PG2S
F25L32QA –50PAG2S
F25L32QA –86PAG2S
F25L32QA –100PAG2S
F25L32QA –50PHG2S
F25L32QA –86PHG2S
Speed
50MHz
86MHz
104MHz
50MHz
86MHz
104MHz
50MHz
86MHz
16-lead
SOIC
300 mil
Pb-free
8-lead
SOIC
200 mil
Pb-free
8-lead
SOIC
150 mil
Pb-free
Package
Comments
F25L32QA –100PHG2S 104MHz
F25L32QA –50HG2S
F25L32QA –86HG2S
F25L32QA –100HG2S
50MHz
86MHz
104MHz
8-contact
WSON
6x5 mm
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.7
1/51
ESMT
F25L32QA (2S)
is divided into 1,024 uniform sectors with 4K byte each; 128
uniform blocks with 32K byte each; 64 uniform blocks with 64K
byte each. Sectors can be erased individually without affecting
the data in other sectors. Blocks can be erased individually
without affecting the data in other blocks. Whole chip erase
capabilities provide the flexibility to revise the data in the device.
The device has Sector, Block or Chip Erase but no page erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
GENERAL DESCRIPTION
The F25L32QA is a 32Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual/Quad SPI. ESMT’s
memory devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 16,384 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The device features sector erase architecture. The memory array
FUNCTIONAL BLOCK DIAGRAM
Page Address
Latch / Counter
High Voltage
Generator
Memory
Array
Page Buffer
Status
Register
Byte Address
Latch / Counter
Y-Decoder
Command and Conrol Logic
Serial Interface
CE
SCK
SI
(SIO
0
)
SO
WP
HOLD
(SIO
1
) (SIO
2
) (SIO
3
)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.7
2/51
ESMT
F25L32QA (2S)
PIN CONFIGURATIONS
8-Lead SOIC
(SOIC 8L, 150mil Body, 1.27mm Pin Pitch)
(SOIC 8L, 208mil Body, 1.27mm Pin Pitch)
CE
1
8
V
DD
SO / SIO
1
2
7
HOLD / SIO
3
WP / SIO
2
3
6
SCK
V
SS
4
5
SI / SIO
0
16-Lead SOIC
(SOIC 16L, 300mil Body, 1.27mm Pin Pitch)
HOLD / SIO
3
V
DD
1
2
16
15
SCK
SI / SIO
0
NC
NC
3
4
14
13
NC
NC
NC
NC
5
6
12
11
NC
NC
CE
SO / SIO
1
7
8
10
9
V
SS
WP / SIO
2
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.7
3/51
ESMT
8- Contact WSON
(WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch)
F25L32QA (2S)
CE
1
8
V
DD
SO / SIO
1
2
7
HOLD / SIO
3
WP / SIO
2
3
6
SCK
V
SS
4
5
SI / SIO
0
PIN DESCRIPTION
Symbol
SCK
Pin Name
Serial Clock
Serial Data Input /
Serial Data Input Output 0
Functions
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO
pin to transfer commands, addresses or data serially into the device on the
rising edge of SCK and read data or status from the device on the falling edge
of SCK(for Dual/Quad mode).
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual/Quad
mode).
To activate the device when CE is low.
The Write Protect (
WP
) pin is used to enable/disable BPL bit in the status
register. / Bidirectional IO pin to transfer commands, addresses or data serially
into the device on the rising edge of SCK and read data or status from the
device on the falling edge of SCK (for Quad mode).
To temporality stop serial communication with SPI flash memory without
resetting the device. / Bidirectional IO pin to transfer commands, addresses or
data serially into the device on the rising edge of SCK and read data or status
from the device on the falling edge of SCK (for Quad mode).
To provide power.
SI / SIO
0
SO / SIO
1
Serial Data Output /
Serial Data Input Output 1
Chip Enable
Write Protect /
Serial Data Input Output 2
CE
WP
/ SIO
2
HOLD / SIO
3
V
DD
V
SS
Hold /
Serial Data Input Output 3
Power Supply
Ground
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.7
4/51
ESMT
F25L32QA (2S)
SECTOR STRUCTURE
Table 1: Sector Address Table
64KB
Block
32KB
Block
Sector
1023
127
63
126
:
1016
1015
:
1008
1007
125
62
124
:
1000
999
:
992
991
123
61
122
:
984
983
:
976
975
121
60
120
:
968
967
:
960
959
119
59
118
:
952
951
:
944
943
117
58
116
:
936
935
:
928
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Address range
3FF000H – 3FFFFFH
:
3F8000H – 3F8FFFH
3F7000H – 3F7FFFH
:
3F0000H – 3F0FFFH
3EF000H – 3EFFFFH
:
3E8000H – 3E8FFFH
3E7000H – 3E7FFFH
:
3E0000H – 3E0FFFH
3DF000H – 3DFFFFH
:
3D8000H – 3D8FFFH
3D7000H – 3D7FFFH
:
3D0000H – 3D0FFFH
3CF000H – 3CFFFFH
:
3C8000H – 3C8FFFH
3C7000H – 3C7FFFH
:
3C0000H – 3C0FFFH
3BF000H – 3BFFFFH
:
3B8000H – 3B8FFFH
3B7000H – 3B7FFFH
:
3B0000H – 3B0FFFH
3AF000H – 3AFFFFH
:
3A8000H – 3A8FFFH
3A7000H – 3A7FFFH
:
3A0000H – 3A0FFFH
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
Block Address
A21
A20
A19
A18
A17
A16
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.7
5/51
NXP MCU
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