CH5101A
CHRONTEL
CMOS Monochrome Digital Video Camera
Features
• 352 x 288 monochrom e active pixel array, 1/3 inch lens
format
¥
• Programmable formats CIF 352x288, QCIF 17 6x144,
CCIR601 704x288
• Digital output CCIR601 4:2:2 (8-bit)
• Multidimensional automatic shutter control
• Below 1 LUX sensitivity
• Programmable I
2
C Serial bus control:
-
-
-
-
-
-
-
F ram e ra te : 30fps-1fps in e ight steps
Gam m a c or rec tion
Shutte r spe ed
Ana log gain
16 bac klight com pensation z one s
B la ck clam p level
Power down m odes
Description
The CH5101 is a single chip active p ixel CMOS
mono chrome v ideo cam era with digital video o utput in
several formats. Usin g sophisticated no ise correctio n
circuitry to min imize fixed pattern n oise and dark current
effects, the CH5101 pro vides a supurb quality picture in a
low cost device.
The CH5101 uses a p rop rietary au to shutter algorithm to
dynamically co ntrol th e shu tter time, analog gain, and
black clamp level, providing optimum picture and con trast
under all ligh ting cond itio ns. The CH5101 als o
incorporates extensive on-chip programm ab le digital
signal process ing to max imize the u sefulness o f the d ev ice
in processor driven applications. Th is includes 16
programmable zones for b acklight co mpensation,
allowing the user to adjus t the image to th eir unique
lighting environment.
Additionally, at power-u p the backligh t com pensatio n
zone, power-up condition, and direct A/D outpu t m odes
are selectable without IIC con trol by using the PUD pins .
Req uiring a min imum of parts for operation, th e CH5101
provides a lo w co st cam era fo r the next g en eration
videophone, toy, an d s urv eillance products.
3
• Stand-alone 25fps PAL and 30fps NTSC operation
with all automatic features
• Single crystal operation: Video timing on-chip
• Single 5V power supply
• Less than 0.5 watt power dissipatio n
¥
Patent number x,xxx,xxx patents pending
352
Columns
Photocell
Array
R
O
W
T
I
M
I
N
G
Shutter
Control
I C
BUS
2
SD
SC
AS
288
Rows
Timing
&
Mode
Control
Row Decode
HREF
PDP*
HS*
VS*
CLKOUT
Reset*
XI/Fin
XO
PUD[6:0]
TOUT/TOUTB
OVR
A/D
Gain
Black
Clamp
2-D
LPF
Gamma
Correct
Output
Format
Y[7:0]
Figure 1: Block Diagram
201-0000-033 Rev 1.0, 6/2/99
1
CHRONTEL
CH5101A
RESET*
AS
DVDD
CMB2
AVDD
DGND
TOUTB
DVDD
TOUT
AGND
52 51 50 49 48 47 46 45 44 43 42 41 40
DGND
VS*
HS*
DVDD
OVR
HREF
Y0
Y1
Y2
Y3
Y4
Y5
Y6
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
PUD4*
CLKOUT
DGND
PUD0*
PUD1*
PUD2*
PUD3*
PUD5*
PUD6
Y7
DVDD
NC
NC
39
38
37
36
35
34
33
32
31
30
29
28
27
AVDD
ARF
ARF2
AGND
CRF
VREF
AVDD
XI/FIN
XO
AGND
DGND
PDP*
DVDD
Image Array
Figure 2: 52-Pin PQFP
2
VRS
201-0000-033 Rev 1.0, 6/2/99
SC
SD
CHRONTEL
CH5101A
DVDD
SC
SD
DGND
RESET*
AS
DVDD
CMB2
AVDD
TOUTB
TOUT
AGND
51
50
49
48
47
7
6
5
4
3
2
1
52
VRS
DGND
VS*
HS*
DVDD
OVR
HREF
Y0
Y1
Y2
Y3
Y4
Y5
Y6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
C L K O U T
23
24
DGND
1mm
Image Array
46
45
44
43
42
41
40
40
39
38
37
36
35
34
AVDD
ARF
ARF2
AGND
CRF
VREF
AVDD
XI/FIN
XO
AGND
DGND
PDP*
DVDD
PUD0*
PUD1*
PUD2*
PUD3*
PUD4*
PUD5*
DVDD
PUD6
.600 in Sq
Figure 3: 52 Contact Ceramic LCC (Top View)
201-0000-033 Rev 1.0, 6/2/99
NC
Y7
NC
25
26
27
28
29
30
31
32
33
3
CHRONTEL
CH5101A
60 um
1301 um
Image
Array
3670.3 um
Package
Centerline
CMOS Die
Package
Centerline
4906.7 um
Figure 4: CH5101 Array Image Offset
4
201-0000-033 Rev 1.0, 6/2/99
CHRONTEL
CH5101A
Table 1. Pin Descriptions
Pin
21-14
(14-7)
1,7,11,22,34,
(4,15,27,46,52)
4,8,24,36,
(1, 17, 29, 49)
31-25
(24-18)
Power
D GND
Power
D VDD
Note:
Pin numbers in parenthesis ( ) are for 52 pin PQFP
Sym bol
Desc ription
Video Outpu t
Provides the luminance data of the digital v ideo output.
Digital Sup ply Voltag e
These pins supply the 5V pow er to the digital s ection of CH 5101.
Digital Gro und
Provides the ground referenc e for the digital sec tion of C H5101. These
pins M UST be connected to the sy stem ground.
Type
Out
Y[7:0]
In
PU D[5:0]*
PU D[6]
Power Up Detect (internal p ull-up)
These are inputs c ontrolling the default value of IIC regis ter bits
M 0, ADD O, PD , ASW[3:0]. Attac h 100K Ohm s to D GN D to pull low.
NOTE: PU D[5:0]* are logically inverted
Video Pixel Clock Outpu t
This pin outputs a buffered c loc k s ignal w hic h can be used to latch data
output by pins Y[7:0]
23
(16)
9
(2)
10
(3)
12
(5)
13
(6)
6
(51)
5
(50)
2
(47)
Out
C LKOU T
Out
Out
Out
VS*
H S*
OVR
Ver tical Sync Outpu t (active lo w)
Outputs a v ertical s ync puls e.
Ho riz ontal Sync Ou tp ut (active low)
Outputs a horizontal sync pulse.
Over R an ge
This pin is high when the A/D converter input is bey ond the full sc ale
range of the A/D .
Out
H REF
Ho riz ontal Referen ce
Activ e video tim ing signal. This output is high when activ e data is being
output from the devic e, and low otherwise.
Serial Clock
IIC clock input pin.
Serial Data
IIC data input/output pin.
Ch ip Add ress Select (intern al p ullup )
This pin selects the IIC addres s for the dev ice.
AS = 1 Address = 100 0101
AS = 0 Address = 100 0110
In
In/Out
In
SC
SD
AS
3
(48)
38
(31)
39
(32)
In
R ESET *
Ch ip Reset (active low, intern al p ullup)
Puts all registers into power-on default s tates . T he s tate at pin SD mus t
be HIGH during reset for proper initializ ation.
In/Out
XO
Cr ystal Outpu t
A 27 M Hz (± 50 ppm, parallel res onance) crys tal m ay be attached
between XO and XI/F IN.
In
XI/FIN
Cr ystal In put or Exter nal in put
A 27 M Hz (± 50 ppm, parallel res onance) crys tal s hould be attac hed
between XO and XI/F IN. An external CMOS c ompatible c loc k c an be
connected to XI/FIN as an alternative.
201-0000-033 Rev 1.0, 6/2/99
5
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