Electronics Corp.
Multi-Layer Ceramic Capacitor
C-S1-5-00
C0G (NP0) Dielectrics
Features
A monolithic structure ensures high reliability and mechanical strength.
High capacitance density.
A wide range of capacitance values in standard case size.
Suitable for high speed SMT placement on PCBs.
Ni barrier termination highly resistance to migration.
Lead-free termination is in compliance with the requirement of green plan and ROHS.
S1
Applications
General electronic equipment.
Custom Application
C0G (NP0) Dielectric Characteristics
Capacitance Range
Size (mm)
(EIA inch)
Test Voltage
Test Frequency
Capacitance Tolerance
0.20pF to 39nF
0603
1005
1608
2012
3216
(1206)
(0201) (0402)
1.0 ± 0.2Vrms
(0603) (0805)
1.0 ± 0.2MHz for cap≦1,000pF, 1.0 ± 0.2KHz for cap＞1,000pF
± 0.25pF, ± 0.50pF for cap＜5pF (± 0.1pF available on request)
± 0.50pF for 5pF≦cap＜10pF (± 0.1pF, ± 0.25pF available on request)
± 5%, ± 10% for cap≧10pF (± 1%, ± 2% available on request)
Operating Temperature Range
Maximum Capacitance Change
Rated Voltage
Dissipation Factor (DF)
Insulation Resistance (+25℃, RVDC)
Insulation Resistance (+125℃, RVDC)
-55℃ to +125℃
0 ± 30 ppm/℃ (EIA C0G)
16, 25, 50, 100 VDC
1/(400 + 20 x C) for cap≦30pF, C in pF
；0.1%
max. for cap＞30pF
10,000 MΩ min. or 500Ω-F min., whichever is smaller
1,000 MΩ min. or 50Ω-F min., whichever is smaller
Darfon Product Specification
1
Rev.: 4
Electronics Corp.
Multi-Layer Ceramic Capacitor
Product Range and Thickness
CLASS
TYPE
T.C
SIZE *0603
(EIA) 0201
RV
25V
0.20 p
0.50 p
A
0.75 p
A
1.0 p
A
1.2 p
A
1.5 p
A
1.8 p
A
2.2 p
A
2.7 p
A
3.3 p
A
3.9 p
A
4.7 p
A
5.6 p
A
6.8 p
A
8.2 p
A
10 p
12 p
15 p
18 p
22 p
27 p
33 p
39 p
47 p
56 p
68 p
82 p
100 p
120 p
150 p
180 p
220 p
270 p
330 p
390 p
470 p
560 p
680 p
820 p
1.0 n
1.2 n
1.5 n
1.8 n
2.2 n
2.7 n
3.3 n
3.9 n
4.7 n
5.6 n
6.8 n
8.2 n
10 n
12 n
15 n
18 n
22 n
27 n
33 n
39 n
A
A
A
A
A
A
A
A
A
A
A
A
A
Class I
Standard
C0G (NP0)
1005
0402
25V
50V
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
1608
0603
25V
50V
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
2012
0805
25V
50V
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
E
E
E
E
G
G
G
G
G
G
G
G
G
E
E
G
G
G
G
G
G
G
G
E
E
G
G
G
G
G
G
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
E
E
E
E
G
G
3216
1206
25V
50V
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
F
F
G
G
G
G
G
G
G
L
I
I
G
F
F
I
I
F
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
F
F
L
C-S1-5-00
16V
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
100V
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
16V
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
100V
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
16V
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
E
E
E
E
E
E
100V
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
E
E
E
E
E
E
E
E
E
E
G
G
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
16V
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
I
I
100V
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
Note：Thickness might be changed due to technology improvement.
Darfon Product Specification
2
Rev.: 4
Electronics Corp.
Multi-Layer Ceramic Capacitor
Taping Amount
Thickness
180 mm (7”)
Code
A
B
C
D
D*
E
Spec
0.30+/-0.03
0.50+/-0.05
0.60+/-0.15
0.80+/-0.10
0.80+0.15/ -0.10
0.85+/-0.15
Size(EIA)
0603 (0201)
1005 (0402)
2012 (0805)
3216 (1206)
1608 (0603)
1608 (0603)
2012 (0805)
3216 (1206)
3225 (1210)
4532 (1812)
2012 (0805)
3216(1206)
3216 (1206)
4520 (1808)
2012 (0805)
3216 (1206)
3225 (1210)
4520 (1808)
4532 (1812)
2012 (0805)
3216 (1206)
3225(1210)
3225 (1210)
4520 (1808)
4532 (1812)
3216 (1206)
3225 (1210)
4520 (1808)
4532 (1812)
3216 (1206)
3225 (1210)
4520 (1808)
4532 (1812)
3216 (1206)
3225 (1210)
4520 (1808)
4532 (1812)
3225 (1210)
3225 (1210)
3225 (1210)
Paper
15K
10K
4K
4K
4K
4K
4K
4K
Embossed
Amount per reel
250 mm (10”)
Paper
Embossed
330 mm (13”)
Paper
50K
15K
15K
15K
15K
15K
15K
10K
Embossed
C-S1-5-00
10K
10K
10K
10K
10K
10K
3K
1K
3K
3K
3K
3K
2K/3K
3K
3K
3K
1K
2K/3K
3K
3K
2K
2K
1K
2K
2K
2K
1K
2K
2K
2K
1K
2K/3K
2K
1K
1K
2K
500pcs/1K
500pcs/1K
500pcs
500pcs
I
F
0.95+/-0.15
1.15+/-0.20
10K
10K
10K
G
1.25 +/-0.20
G
1.25+0.3/-0.2
10K
10K
H
1.50+/-0.20
L
1.60+/-0.20
L
1.60+0.30/-0.20
N
N
P
P
R
R
2.00+/-0.20
2.00+/-0.30
2.50+/-0.20
2.50+/-0.30
3.20+/-0.20
3.20+/-0.30
*: For some products, the thickness spec can be 0.8+0.15/-0.1mm.
Darfon Product Specification
3
Rev.: 4
Electronics Corp.
Multi-Layer Ceramic Capacitor
C0G (NP0) Specifications
No.
Item
Specification
1 Operating Temperature Range
-55℃ to 125℃
2
Rated Voltage
16VDC, 25VDC, 50VDC, 100VDC
Test Method
-
C-S1-5-00
S1
3
4
5
Appearance
Dimensions
Dielectric Strength (Flash)
No defects or abnormalities.
Within the specified dimension.
No defects or abnormalities.
The rated voltage is defined as the maximum
voltage, which may be applied continuously to the
capacitor.
Visual inspection
Using calipers
No failure shall be observed when 250% of the
rated voltage is applied between the terminations
for 1 to 5 seconds, the charge and discharge
current is less than 50mA.
The insulation resistance shall be measured with a
DC voltage not exceeding the rated voltage at 25℃
and 75%RH max, and within 1 minute of charging.
The capacitance/D.F. shall be measured at 25℃ at
the frequency and voltage shown in the tables.
Item
C≦1,000pF
＞1,000pF
Frequency 1.0±0.2MHz 1.0±0.2KHz
Voltage 1.0±0.2Vrms 1.0±0.2Vrms
6
Insulation Resistance ( I.R.)
Rated Voltage:
<500V
Rated Voltage:
≧500V
To apply rated
voltage.
To apply 500V.
.R.
≧10G or
R
i
C
R
≧500Ω-F
(whichever is smaller)
7
8
Capacitance
Dissipation Factor ( D.F.)
Within the specified tolerance.
If C＞30pF, DF≦0.1%
If C≦30pF, DF≦1/(400+20C), C in pF
Temperature compensating type: The capacitance
value at 25℃ and 85℃ shall be measured and
calculated from the formula given below.
6
T.C.=(C
85
-C
25
)/C
25
*ΔT*10 (PPM/℃)
10 Termination Strength
No removal of the terminations or marking Apply a parallel force of 5N to a PCB mounted
defect.
sample for 10±1sec. *2N for 0603 (EIA 0201).
Solder the capacitor to the test jig (glass epoxy
11 Deflection (Bending Strength)
Appearance: No cracking or marking
boards) shown in Fig. a. using a eutectic solder.
defects.
Capacitance change: within ±5% or ± 0.5pF. Then apply a force in the direction shown in Fig. b.
The soldering shall be done with the reflow method
(whichever is larger)
and shall be conducted with care so that the
soldering is uniform and free of defects such as
heat shock.
(Unit in mm)
b
9
Capacitance Temperature
Characteristics
Capacitance change within 0±30ppm/℃
under operating temperature range.
φ
4.5
Size
a
0.3
0.4
1.0
1.2
2.2
b
0.9
1.5
3.0
4.0
5.0
C
0.3
0.5
1.2
1.65
2.0
R230
20 50 Pressurizing speed : 1.0mm/sec.
Pressurize
c
a
40
0603
1005
1608
2012
3216
Flexure : 1mm
Capacitance Meter
100
t :1.6mm(0.8mm for 0603&1005 size)
45
45
Fig. a.
Fig. b.
12 Solderability of Termination
13 Resistance to Appearance
Soldering Heat Cap. Change
D.F.
I.R.
Immerse the test capacitor into a methanol solution
containing rosin for 3 to 5 seconds, preheat it 150
to 180℃ for 2 to 3 minutes and immerse it into
molten solder of 230 ± 5℃ for 5±1seconds.
Preheat the capacitor at 120 to 150℃ for 1 minute.
No marking defects
NP0 within ±2.5% or ±0.25pF. (whichever is Immerse the capacitor in an eutectic solder solution
at 270±5℃ for 10±1 seconds. Let sit at room
larger)
temperature for 24±2 hours, then measure.
If C＞30pF, DF≦0.1%
* Preheat at 150 to 200℃ for size≧3216
If C≦30pF, DF≦1/(400+20C), C in pF
I.R.≧10,000MΩ or R
i
C
R
≧500Ω-F.
( whichever is smaller)
90% of the termination is to be soldered
evenly and continuously.
Darfon Product Specification
4
Rev.: 4
Electronics Corp.
Multi-Layer Ceramic Capacitor
Continued from previous page.
14 Temperature
Cycle
(Thermal
Shock)
Appearance
Cap. Change
D.F.
I.R.
Solder the capacitor to supporting jig (glass epoxy
board) and perform the five cycles according to the
NP0 within ±2.5% or ±0.25pF. (whichever is four heat treatments listed in the following table. Let
larger)
sit for 24±2hrs at room temperature, then measure.
If C＞30pF, DF≦0.1%
If C≦30pF, DF≦1/(400+20C), C in pF
Step 1: Minimum operating temperature 30±3min
More than 10,000MΩ or R
i
C
R
＞500Ω-F
Step 2: Room temperature
2~3 min
( whichever is smaller )
Step 3: Maximum operating temperature 30±3min
No marking defects
Step 4: Room temperature
15 Humidity Load Appearance
Cap. Change
D.F.
I.R.
No marking defects
2~3min
C-S1-5-00
S1
Apply the rated voltage at 40±2℃ and 90 to 95%
humidity for 500±12 hours. Remove and let sit for
NP0 within ±7.5% or ±0.75pF. (whichever is
24±2 hours at room temperature, then measure.
larger)
The charge/discharge current is less than 50mA.
If C＞30pF, DF≦0.5%
If C≦30pF, DF≦1/(100+10xC/3), C in pF
More than 500MΩ or R
i
C
R
≧25Ω-F.
(whichever is smaller)
Apply 200% of the rated voltage for 500±12 hours
at the maximum operating temperature ± 3℃. Let
NP0 within ±7.5% or ±0.75pF (whichever is sit for 24± 2 hours at room temperature, then
large)
measure. The charge/discharge current is less than
If C＞30pF, DF≦0.3%
50mA.
If 10pF＜C≦30pF, DF≦1/(275+5xC/2)
If C≦10pF, DF≦1/(200+10C), C in pF
More than 1 GΩ or R
i
C
R
≧50Ω-F.
(whichever is smaller)
No marking defects
16 High
Temperature
Load
(Life Test)
Appearance
Cap. Change
D.F.
I.R.
Darfon Product Specification
5
Rev.: 4
FPGA/CPLD
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