UTRON
Rev. 1.0
UT62L12916/UT62L12916(I)
128K X 16 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
DESCRIPTION
Preliminary Rev. 0.5 Original.
Rev.1.0
1. Revised Features
-Access time 70/100ns 55/70/100ns
-Operating current 5mA(Icc1,max) 45/35/25mA(Icc max)
-Standby current 80/25uA(max) 20/2uA(typ)
-Vcc power supply 2.7~3.3V 2.5~3.6V
2. Revised Function block diagram
3. Revised DC electrical characteristics table
4. Revised AC electrical characteristics table
5. Revised Timing waveforms
6. Revised Data retention characteristics table & waveform
7. Revised 48 TFBGA outline dimension, ball size 0.3mm 0.35mm
8. Revised order information
Date
Mar, 2001
May 15,2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80042
1
UTRON
Rev. 1.0
UT62L12916/UT62L12916(I)
128K X 16 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L12916 is a 2,097,152-bit low power CMOS
static random access memory organized as 131,072
words by 16 bits.
The UT62L12916 operates from a single 2.5V ~ 3.6V
power supply and all inputs and outputs are fully TTL
compatible.
The UT62L12916 is designed for low power system
applications. It is particularly well suited for use in
high-density low power system applications.
FEATURES
Fast access time :
55ns (max.) for Vcc=2.7V~3.6V
70/100ns (max.) for Vcc=2.5V~3.6V
CMOS low power operating
Operating current : 45/35/25mA (Icc max.)
Standby current : 20uA(max.) L–version
2uA(max.) LL-version
Single 2.5V~3.6V power supply
Operating temperature:
Commercial : 0
℃
~70
℃
Industrial : -40
℃
~85
℃
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min.)
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 48-pin 6mm × 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
128K X 16
MEMORY
ARRAY
A0-A17
DECODER
Vcc
Vss
I/O1-I/O8
Lower Byte
I/O9-I/O16
Upper Byte
I/O DATA
CIRCUIT
COLUMN I/O
CE2
CE
OE
WE
LB
UB
CONTROL
CIRCUIT
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80042
2
UTRON
Rev. 1.0
UT62L12916/UT62L12916(I)
128K X 16 BIT LOW POWER CMOS SRAM
PIN DESCRIPTION
SYMBOL
A0 - A17
I/O1 - I/O16
CE
, CE2
WE
OE
LB
UB
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-byte Control
Upper-byte Control
Power Supply
Ground
No Connection
PIN CONFIGURATION
A
LB
OE
A0
A1
A2
CE2
B
I/O 9
UB
A3
A4
CE
I/O 1
C
I/O 1 0
I/O 1 1
A5
A6
I/O 2
I/O 3
D
V ss
I/O 1 2
NC
A7
I/O 4
V cc
E
V cc
F
I/O 1 5
G
I/O 1 6
H
NC
A8
A9
A10
A11
NC
C IO S
A12
A13
WE
I/O 8
I/O 1 4
A14
A15
I/O 6
I/O 7
I/O 1 3
NC
A16
I/O 5
V ss
1
2
3
4
5
6
TFBGA
TRUTH TABLE
MODE
CE
CE2
OE
WE
LB
UB
X
X
H
X
L
H
L
L
H
L
L
H
X
X
Standby
X
L
X
X
X
X
L
H
H
Output Disable
L
H
H
L
H
L
Read
L
H
L
L
H
L
L
H
X
Write
L
H
X
L
H
X
Note: H = V
IH
, L=V
IL
, X = Don't care.
X
X
X
H
H
H
H
H
L
L
L
X
X
H
L
X
L
H
L
L
H
L
I/O OPERATION
I/O1-I/O8
I/O9-I/O16
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
D
OUT
High – Z
D
OUT
High – Z
D
OUT
D
OUT
High – Z
D
IN
D
IN
High – Z
D
IN
D
IN
SUPPLY
CURRENT
I
SB
, I
SB1
I
CC
,I
CC1
,I
CC2
I
CC
,I
CC1
,I
CC2
I
CC
,I
CC1
,I
CC2
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80042
3
UTRON
Rev. 1.0
UT62L12916/UT62L12916(I)
128K X 16 BIT LOW POWER CMOS SRAM
SYMBOL
V
TERM
T
A
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.6
0 to 70
-40 to 85
-65 to 150
1
50
260
UNIT
V
℃
℃
℃
W
mA
℃
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Commercial
Operating Temperature
Industrial
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(T
A
= 0
℃
to 70
℃
/-40
℃
to 85
℃
(I))
PARAMETER
Power Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Operating Power
Supply Current
Average Operation
Current
Standby Current (TTL)
Standby Current (CMOS)
SYMBOL
TEST CONDITION
V
CC
V
IH
＊
2
V
IL
I
LI
I
LO
V
OH
V
OL
I
CC
I
CC1
I
CC2
I
SB
I
SB1
CE =V
IH,
other pins =V
IL
or V
IH
CE =V
CC
-0.2V
other pins at 0.2V or Vcc-0.2V
＊
1
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC;
Output Disable
I
OH
= -1mA
I
OL
= 2.1mA
Cycle time=min, 100%duty
I/O=0mA, CE =V
IL
100%duty,I
I/O
=0mA, CE
≦
0.2V,
other pins at 0.2V or Vcc-0.2V
MIN. TYP. MAX. UNIT
55
2.7 3.0
3.6
V
70/100 2.5
-
3.6
V
V
2.2
-
V
CC
+0.3
-0.2
-
0.6
V
-1
-
1
µA
-1
-
1
µA
2.2
-
-
V
-
-
0.4
V
55
-
30
45
mA
70
-
25
35
mA
100
-
20
25
mA
Tcycle=
-
4
5
mA
1µs
Tcycle=
-
8
10
mA
500ns
-
0.3
0.5
mA
-L
-
20
80
µA
-LL
-
2
20
µA
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80042
4
UTRON
Rev. 1.0
UT62L12916/UT62L12916(I)
128K X 16 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 30pF, I
OH
/I
OL
= -1mA/2.1mA
AC ELECTRICAL CHARACTERISTICS
(T
A
= 0
℃
to 70
℃
/-40
℃
to 85
℃
(I))
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
LB
,
UB
Access Time
LB
,
UB
to High-Z Output
LB
,
UB
to Low-Z Output
SYMBOL
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
t
BA
t
BHZ
t
BLZ
UT62L12916-55
UT62L12916-70
UT62L12916-100
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
55
-
-
-
10
5
-
-
10
-
-
10
MAX.
-
55
55
30
-
-
20
20
-
55
25
-
MIN.
70
-
-
-
10
5
-
-
10
-
-
10
MAX.
-
70
70
35
-
-
25
25
-
70
30
-
MIN.
100
-
-
-
10
5
-
-
10
-
-
10
MAX.
-
100
100
50
-
-
30
30
-
100
40
-
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
LB
,
UB
Valid to End of Write
SYMBOL
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
t
BW
UT62L12916-55
UT62L12916-70
UT62L12916-100
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
55
50
50
0
45
0
25
0
5
-
45
MAX.
-
-
-
-
-
-
-
-
-
30
-
MIN.
70
60
60
0
55
0
30
0
5
-
60
MAX.
-
-
-
-
-
-
-
-
-
30
-
MIN.
100
80
80
0
70
0
40
0
5
-
80
MAX.
-
-
-
-
-
-
-
-
-
40
-
* These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80042
5
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