Form No.: QF-1274
Edition: 2
SPECIFICATION FOR APPROVAL
Customer：
Customer P/N:
Drawing No：
Quantity：
Chilisin P/N：
0
Pcs.
Date：
ACTR Series
2021/7/15
Automotive Grade Resistor
Halogen Free
RoHS Compliant
REACH Compliant
Lead Free Solders
AEC-Q200
奇力新電子股½有限公司
Chilisin Electronics Corp
No. 29, Alley 301, Tehhsin Rd., Hukou,Hsinchu
303, Taiwan
TEL：+886-3- 599-2646
FAX：+886-3- 599-9176
E-mail：sales@chilisin.com
http：//www.chilisin.com
東莞奇力新電子(東莞廠)有限公司
Chilisin Electronics (Dongguan) Co., Ltd.
No. 78, Puxing Rd., Yuliangwei Administration Area,
Qingxi Town, Dongguan City, Guangdong,China
TEL：+86-769-8773-0251~3
FAX： +86-769-8773-0232
E-mail：cect@chilisin.com
奇力新電子(越南廠)有限公司
Chilisin Electronics (Vietnam) Limited
No 143 - 145, Road No 10, VSIP Hai Phong,
Lap Le Commune, Thuy Nguyen Dist,
Haiphong City, Vietnam
奇力新電子(湖南廠)有限公司
HuNan Chilisin Electronics Technology Co., Ltd
No. 8, Shaziao Liangshuijing Town, Yuanling County,
Huaihua City, Hunan Province 419601, China
Tel：86-745-867-5882
Drawn by
Checked by
Approved by
Desmond.Wu
Cf.Hsieh
Wl.Liu
ACTR Series Specification
6 Reliability Test:
No
Item
Conditions
Put the specimens in the chamber with temperature of
155±3℃ for 1000 hours. Then take them out to stabilize
in room temperature for 24±4hr or more, and measure of
its resistance variance rate.
Experiment evidence: AEC-Q200
Put the specimens in the High & low temperature test
chamber with temperature varies from -55℃ to 125℃
for 15 minutes and total 1000 cycles. Then take them out
to stabilize in room temperature for 24±4hr or more, and
measure of its resistance variance rate.
Experiment evidence: AEC-Q200
Applied 2.5 times rated voltage for 5 seconds and
release the load for about 30 minutes, then measure its
resistance variance rate.
(Rated voltage refer to item 3. general specifications)
Refer to JIS-C5201-1 4.13
Solder the specimens on the test PCB and put them into
the constant temperature humidity chamber with 85±2℃
and 85±5%RH. Then apply the test voltage that
calculates based on the 10% of rated power for 1000hrs.
Then take them out to stabilize in room temperature for
24±4hr or more, and measure of its resistance variance
rate.
Experiment evidence: AEC-Q200
Solder the specimens on the test PCB and Put them in
the chamber with temperature of 125±3℃ and load the
rated voltage for 1000 hours. Then take them out to
stabilize in room temperature for 24±4hr or more, and
measure of its resistance variance rate.
Experiment evidence: AEC-Q200
The specimens are fully immersed into the Pb-free
solder pot, then take them out to stabilize for 1 hour or
more and measure of its resistance variance rate.
Temp of solder pot：260±5℃
Soldering duration：10±1sec.
Experiment evidence AEC-Q200
Put the specimens on the test fixture and two
(2)discharges (2KVDC) shall be applied to each PUT,
one (1) with a positive polarity and one (1) with a
negative polarity. Afterwards, the specimens stabilize for
30min or more and measure of its resistance variance
rate. The test is performed with direct contact and
regular discharge mode. The resistor and capacitor used
on the spearhead is 2000Ω and 150pF respectively.
Experiment evidence AEC-Q200
Test method:
Test item 1 (solder pot test): Method B
Precondition:
The specimens are subjected to 155℃ dry bake
for 4hrs±15min.
The specimens are immersed into the flux first, then fully
immersed into the solder pot, at a temperature of 235± 5℃
for 5+0/-0.5 sec. Then rinse with water and observe the
soldering coverage under the microscope.
Test item 2 (Leaching test): Method D
The specimens are immersed into the flux first, then fully
immersed into the solder pot, at a temperature of
260±5℃ for 30+0/-0.5 sec. Then rinse with water and
observe the soldering coverage under the microscope.
Experiment evidence AEC-Q200
△R%=±1.0%
Specifications
Resistors
1-1 High Temperature Exposure
(Storage)
1-2 Temperature Cycling
△R%=±1.0%
1-3 Short Time Overload
△R%=±1.0%
1-4 Biased Humidity
△R%=±2.0%
1-5 Operational Life
△R%=±2.0%
1-6 Resistance to Soldering Heat
△R%=±1.0%
1-7 ESD
△R%=±3.0%
1-8 Solderability
1.Soldering coverage over 95%
2.At the edge of terminal, the object underneath (e.g. white
ceramic) shall not expose.
FPGA/CPLD
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