UTRON
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L25616(I) is a 4,194,304-bit low power
CMOS static random access memory organized as
262,144 words by 16 bits.
The UT62L25616(I) operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are fully
TTL compatible.
The UT62L25616(I) is designed for low power system
applications. It is particularly suited for use in
high-density high-speed system applications.
UT62L25616(I)
FEATURES
Fast access time : 55/70/100 ns
CMOS Low operating power
Operating current: 45/35/25mA (Icc max)
Standby current: 20 uA(TYP.) L-version
3 uA(TYP.) LL-version
Single 2.7V~3.6V power supply
Operating temperature:
Industrial : -40
℃
~85
℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 44-pin 400mil TSOP
Ⅱ
48-pin 6mm × 8mm TFBGA
PIN DESCRIPTION
SYMBOL
A0 - A17
I/O1 - I/O16
CE
WE
OE
LB
UB
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-Byte Control
High-Byte Control
Power Supply
Ground
No Connection
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A8
A13
A14
A15
A16
A17
I/O1
I/O16
ROW
DECODER
.
MEMORY ARRAY
VCC
VSS
.
.
2048 Rows x 128 Columns x 16 bits
.
.
.
.
I/O
CONTROL
.
.
.
.
.
.
.
.
COLUMN I/O
CE
WE
OE
LOGIC
CONTROL
COLUMN DECODER
LB
UB
A9 A10 A11 A12 A5 A6 A7
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80054
1
UTRON
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UT62L25616(I)
PIN CONFIGURATION
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
1
2
3
4
44
43
42
41
A5
A6
A7
OE
UB
A
B
C
D
E
F
G
H
LB
I/O9
I/O10
OE
UB
I/O11
I/O12
I/O13
A0
A3
A5
A17
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE
I/O2
I/O4
I/O5
I/O6
NC
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
NC
UT62L25616(I)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A12
Vss
Vcc
I/O15
I/O16
I/O14
NC
A8
WE
A11
NC
A17
A16
A15
A14
A13
1
2
3
4
5
6
TFBGA
TSOP II
TRUTH TABLE
MODE
Standby
Output
Disable
Read
CE
OE
X
X
H
X
L
L
L
X
X
X
WE
LB
UB
X
H
X
H
H
L
L
H
L
L
Write
H
X
L
L
L
L
L
L
L
L
X
X
H
X
H
H
H
L
L
L
X
H
X
H
L
H
L
L
H
L
I/O OPERATION
I/O1-I/O8
I/O9-I/O16
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
D
OUT
High – Z
High – Z
D
OUT
D
OUT
D
OUT
D
IN
High – Z
High – Z
D
IN
D
IN
D
IN
SUPPLY CURRENT
I
SB
, I
SB1
I
SB
, I
SB1
I
CC
,I
CC1
,I
CC2
I
CC
,I
CC1
,I
CC2
I
CC
,I
CC1
,I
CC2
Note:
H = V
IH
, L=V
IL
, X = Don't care.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80054
2
UTRON
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UT62L25616(I)
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Industrial
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.6
-40 to 85
-65 to +150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V, TA = -40
℃
to 85
℃
(I))
PARAMETER
SYMBOL
TEST CONDITION
Power Voltage
V
CC
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Leakage Current
I
LI
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current
I
LO
V
SS
≦
V
I/O
≦
V
CC;
Output Disabled
Output High Voltage
V
OH
I
OH
= -1mA
Output Low Voltage
V
OL
I
OL
= 2.1mA
Operating Power
I
CC
Cycle time=min, 100%duty,
Supply Current
I/O=0mA, CE =V
IL
;
Average Operation
Current
Icc1
Icc2
Standby Current (TTL)
Standby Current (CMOS)
I
SB
I
SB1
MIN. TYP. MAX. UNIT
2.7 3.0
3.6
V
2.0
-
V
CC
+0.3
V
-0.2
-
0.6
V
-1
-
1
µA
-1
-
1
µA
2.2
-
-
V
-
-
0.4
V
55 -
30
45
mA
70 -
25
35
mA
100 -
20
25
mA
-
4
5
mA
Cycle time=1µs,100%duty,I/O=0mA,
CE
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
Cycle time=500ns,100%duty,I/O=0mA,
-
8
10
mA
CE
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
-
0.3
0.5
mA
CE =V
IH,
other pins =V
IL
or V
IH
,
CE =V
CC
-0.2V,
other pins at 0.2V or Vcc-0.2V,
-L
-LL
-
-
20
3
80
25
µA
µA
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80054
3
UTRON
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UT62L25616(I)
CAPACITANCE
(TA=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 30pF, I
OH
/I
OL
= -1mA / 2.1mA
AC ELECTRICAL CHARACTERISTICS
(VCC =2.7V~3.6V, TA = -40
℃
to 85
℃
(I))
(1) READ CYCLE
SYMBOL UT62L25616(I)-55 UT62L25616(I)-70 UT62L25616(I)-100 UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
t
RC
55
-
70
-
100
-
ns
Address Access Time
t
AA
-
55
-
70
-
100
ns
Chip Enable Access Time
t
ACE
-
55
-
70
-
100
ns
Output Enable Access Time
t
OE
-
30
-
35
-
50
ns
Chip Enable to Output in Low Z
t
CLZ*
10
-
10
-
10
-
ns
Output Enable to Output in Low Z
t
OLZ*
5
-
5
-
5
-
ns
Chip Disable to Output in High Z
t
CHZ*
-
20
-
25
-
30
ns
Output Disable to Output in High Z
t
OHZ*
-
20
-
25
-
30
ns
Output Hold from Address Change
t
OH
5
-
5
-
5
-
ns
t
BA
-
55
-
70
-
100
ns
LB
,
UB
Access Time
t
HZB
-
25
-
30
-
40
ns
LB
,
UB
to High-Z Output
t
LZB
0
-
0
-
0
-
ns
LB
,
UB
to Low-Z Output
(2) WRITE CYCLE
SYMBOL UT62L25616(I)-55 UT62L25616(I)-70 UT62L25616(I)-100 UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write Cycle Time
t
WC
55
-
70
-
100
-
ns
Address Valid to End of Write
t
AW
50
-
60
-
80
-
ns
Chip Enable to End of Write
t
CW
50
-
60
-
80
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Write Pulse Width
t
WP
45
-
55
-
70
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Data to Write Time Overlap
t
DW
25
-
30
-
40
-
ns
Data Hold from End of Write Time
t
DH
0
-
0
-
0
-
ns
Output Active from End of Write
t
OW*
5
-
5
-
5
-
ns
Write to Output in High Z
t
WHZ*
-
30
-
30
-
40
ns
t
BW
45
-
60
-
80
-
ns
LB
,
UB
Valid to End of Write
*These parameters are guaranteed by device characterization, but not production tested.
PARAMETER
PARAMETER
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80054
4
UTRON
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UT62L25616(I)
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
t
AA
t
OH
t
OH
DOUT
Data Valid
READ CYCLE 2
(
CE
and
OE
Controlled)
(1,3,5,6)
t
Address
RC
CE
t
AA
t
ACE
t
t
BA
LB , UB
BLZ
OE
t
t
Dout
HIGH-Z
CLZ
OE
t
t
t
OH
CHZ
OHZ
t
OLZ
HIGH-Z
Data Valid
t
BHZ
Notes :
WE
is HIGH for read cycle.
2. Device is continuously selected CE =V
IL.
1.
3. Address must be valid prior to or coincident with CE transition; otherwise t
AA
is the limiting parameter.
4. OE is LOW.
5. t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
= 5pF. Transition is measured
±500mV
from steady state.
6. At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80054
5
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