UTRON
Rev. 1.1
UT62L5128(I)
512K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
Preliminary Rev. 0.5
Preliminary Rev. 0.6
Preliminary Rev. 0.7
DESCRIPTION
Original.
1. The symbols CE# and OE# and WE# are revised as. CE
and OE and
WE
.
2. Separate Industrial and Consumer SPEC.
3. Add access time 55ns range.
1. Add SOP and STSOP package
1. Revised 36-pin TFBGA package outline dimension：
a、 Rev. 0.7 : ball diameter=0.3mm
b、 Rev. 0.8 : ball diameter=0.35mm
2. Revised DC ELECTRICAL CHARACTERISTICS：
a、
Revised V
IH
as 2.2V
DATE
Mar, 2001
Jun 21,2001
Dec 18,2001
Preliminary Rev. 0.8
Apr 30,2002
Rev. 1.0
Rev. 1.1
1. Revised Fast access time : 55/70/100ns
55ns (max.) for Vcc=3.0V~3.6V
70/100ns (max.) for Vcc=2.7V~3.6V
2.
Revised Output Disable to Output in High Z (
t
OHZ*
) : 30 35ns
1. Revised Operation surrent :
-Icc(max) 45/35/25mA 40/30/25mA
-Icc(Typ) 30/25/20mA 30/20/16mA
2. Revised Standby current : 20/3uA 20/2uA
3. Revised V
OH
(Typ) : NA 2.7V
4. Add V
IH
(max)=V
CC
+2.0V for pulse width less than 10ns.
V
IL
(min)=V
SS
-2.0V for pulse width less than 10ns.
5. Revised AC Table t
OHZ*
characteristics
6. Add order information for lead free product
Aug 30,2002
May 06,2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80052
1
UTRON
Rev. 1.1
UT62L5128(I)
512K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L5128(I) is a 4,194,304-bit low power CMOS
static random access memory organized as 524,288
words by 8 bits. It is fabricated using high performance,
high reliability CMOS technology.
The UT62L5128(I) operates from a wide range
2.7V~3.6V power supply and supports industrial
operating temperature range.
The UT62L5128(I) is designed for high density and low
power memory applications. The device has a data
retention mode that guarantees data to remain valid at
a minimum power supply voltage of 1.5V.
FEATURES
Fast access time : 55/70/100ns
CMOS Low power operating
Operating current : 40/30/25mA (Icc max.)
Standby current : 20µA (typ.) L-version
2µA (typ.) LL-version
Single 2.7V~3.6V power supply
Industrial Temperature : -40
℃
~85
℃
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min)
Package : 32-pin 450mil SOP
32-pin 8mm × 20mm TSOP-I
32-pin 8mm × 13.4mm STSOP
36-pin 6mm × 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
512K
×
8
MEMORY
ARRAY
A0-A18
DECODER
Vcc
Vss
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80052
2
UTRON
Rev. 1.1
UT62L5128(I)
512K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
A
B
C
D
E
F
G
H
A0
I/O5
I/O6
Vss
Vcc
I/O7
I/O8
A9
A1
A2
NC
WE
NC
A3
A4
A5
A6
A7
A8
I/O1
I/O2
Vcc
Vss
A17
OE
CE
A18
A16
A12
A15
A13
I/O3
I/O4
A14
A10 A11
1
2
3
4
5
6
SOP
TFBGA
A11
A9
A8
A13
WE
A17
A15
Vcc
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP-1 / STSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
PIN DESCRIPTION
SYMBOL
A0 - A18
I/O1 - I/O8
CE
WE
OE
Vcc
Vss
NC
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80052
3
UTRON
Rev. 1.1
UT62L5128(I)
512K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Industrial
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.6
-40 to 85
-65 to 150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O OPERATION
High – Z
High – Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
, I
SB1
I
CC ,
I
CC1,
I
CC2
I
CC ,
I
CC1,
I
CC2
I
CC ,
I
CC1,
I
CC2
H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V, T
A
= -40
℃
to 85
℃
)
PARAMETER
Power Voltage
SYMBOL
V
CC
TEST CONDITION
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Operating Power
Supply Current
Average Operation
Current
Standby Current (TTL)
Standby Current (CMOS)
V
IH
*2
V
IL
I
LI
I
LO
V
OH
V
OL
I
CC
I
CC1
I
CC2
I
SB
I
SB1
*1
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC;
Output Disable
I
OH
= -1mA
I
OL
= 2.1mA
Cycle time=min, 100%duty
I
I/O
=0mA, CE =V
IL
100% duty, I
I/O=
0mA,
CE
≦
0.2,
other pins at 0.2V or Vcc-0.2V
55
70
100
TCycle=
1µs
Tcycle=
500ns
MIN. TYP. MAX. UNIT
2.7 3.0
3.6
V
2.2
-
V
CC
+0.3
V
-0.2
-
0.6
V
-1
-
1
µA
-1
-
1
µA
2.2 2.7
-
V
-
-
0.4
V
-
mA
30
40
-
mA
20
30
-
16
25
mA
-
-
-
4
8
0.3
20
2
5
10
0.5
80
20
mA
mA
mA
µA
µA
CE =V
IH,
other pins = V
IH
or V
IL
CE =V
CC
-0.2V
other pins at 0.2V or Vcc-0.2V
-L
-LL
-
-
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80052
4
UTRON
Rev. 1.1
UT62L5128(I)
512K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 30pF+1TTL , I
OH
/I
OL
= -1mA / 2.1mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V , T
A
= -40
℃
to 85
℃
)
(1) READ CYCLE
UT62L5128(I)-100
SYMBOL UT62L5128(I)-55 UT62L5128(I)-70
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
t
RC
55
-
70
-
100
-
ns
Address Access Time
t
AA
-
55
-
70
-
100
ns
Chip Enable Access Time
t
ACE
-
55
-
70
-
100
ns
Output Enable Access Time
t
OE
-
30
-
35
-
50
ns
Chip Enable to Output in Low Z
t
CLZ*
10
-
10
-
10
-
ns
Output Enable to Output in Low Z
t
OLZ*
5
-
5
-
5
-
ns
Chip Disable to Output in High Z
t
CHZ*
-
20
-
25
-
30
ns
Output Disable to Output in High Z
t
OHZ*
-
20
-
25
-
30
ns
Output Hold from Address Change
t
OH
10
-
10
-
10
-
ns
PARAMETER
(2) WRITE CYCLE
SYMBOL UT62L5128(I)-55 UT62L5128(I)-70 UT62L5128(I)-100 UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write Cycle Time
t
WC
55
-
70
-
100
-
ns
Address Valid to End of Write
t
AW
50
-
60
-
80
-
ns
Chip Enable to End of Write
t
CW
50
-
60
-
80
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Write Pulse Width
t
WP
45
-
55
-
70
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Data to Write Time Overlap
t
DW
25
-
30
-
40
-
ns
Data Hold from End of Write Time
t
DH
0
-
0
-
0
-
ns
Output Active from End of Write
t
OW*
5
-
5
-
5
-
ns
Write to Output in High Z
t
WHZ*
-
30
-
30
-
40
ns
PARAMETER
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80052
5
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