$ %
SRAM
FEATURES
M21L216128A
128 K x 16 SRAM
HIGH SPEED CMOS SRAM
ORDERING INFORMATION
44-pin 400mil SOJ
44-pin 400mil TSOP (TypeII)
Acess Time
(ns)
10
T
T
T
T
T
T
T
T
T
T
Fast access times : 10, 12, and 15ns
Fast
OE
access times : 5, 6, and 7ns
Single +3.3V
±
0.3V power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise immunity
Easy memory expansive with
CE
and
OE
options
Automatic
CE
power down
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PRODUCT NO.
M21L216128A-10J
M21L216128A-10T
M21L216128A-12J
M21L216128A-12T
M21L216128A-15J
M21L216128A-15T
PACKING
TYPE
SOJ
TSOP
12
SOJ
TSOP
SOJ
TSOP
15
GENERAL DESCRIPTION
The M21L216128A is a high speed, low power
asynchronous SRAM containing 2,097,152 bits and
organized as 131,072 by 16 bits, it is produced by high
performance CMOS process.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enable (
CE
), separate byte
enable controls (
LB
and
HE
) and output enable (
OE
) with this
organization.
PIN ASSIGNMENT
SOJ Top View
A4
A3
A2
A1
A0
CE
D Q1
D Q2
D Q3
DQ4
VCC
GND
DQ5
DQ6
DQ7
DQ8
WE
A16
A15
A14
A13
A12
TSOP (TypeII) Top View
A5
A6
A7
OE
HB
LB
DQ 16
DQ 15
DQ 14
DQ 13
GND
VC C
DQ 12
DQ 11
DQ 10
D Q9
NC
A8
A9
A10
A11
NC
A4
A3
A2
A1
A0
CE
D Q1
D Q2
D Q3
D Q4
VC C
GND
DQ5
DQ6
DQ7
DQ8
WE
A1 6
A1 5
A1 4
A1 3
A1 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
HB
LB
DQ16
DQ15
DQ14
DQ13
GND
VCC
DQ12
DQ11
DQ10
D Q9
NC
A8
A9
A1 0
A1 1
NC
Elite Semiconduture Memory Technology Inc
Publication Date
:
Sep. 2000
Revision
:
1.0
1/14
$ %
Block Diagram
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M21L216128A
512 X 4096
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MEMORY ARRAY
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Pin Descriptions
Pin No.
1 - 5, 18 - 22,
24-27, 42 - 44
6
7 - 10, 13 - 16,
29 - 32, 35 - 38
17
39
40
Symbol
A0 - A16
CE
Description
Address Inputs
Chip Enable Input
DQ1 - DQ16
WE
LB
HB
Data Inputs/Outputs
Write Enable Input
Lower Byte Enable Input (DQ1 to DQ8)
Higher Byte Enable Input (DQ9 to
DQ16)
Output Enable Input
Power
Ground
No Connection
41
11, 33
12, 34
23, 28
OE
VCC
GND
NC
Elite Semiconduture Memory Technology Inc
Publication Date
:
Sep. 2000
Revision
:
1.0
2/14
$ %
ABSOLUTE MAXIMUM RATINGS *
Voltage on V
CC
Supply Relative to Vss … ……-0.5V to +4.6V
V
IN
…………………………………………..….-0.5V to V
CC
+1.0V
Operating Temperature, Topr ………………….. 0
°
C to +70
°
C
Storage Temperature (plastic) ……………….-55
°
C to +125
°
C
Junction Temperature ……………………………………+125
°
C
Power Dissipation …..…………………………………….…1.0W
Short Circuit Output Current ………………………………50mA
M21L216128A
*Stresses greater than those listed under Absolute
Maximum. Ratings may permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATIONS
(All Temperature Ranges ; V
CC
= 3.3V
±
0.3V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
0V
≤
V
IN
≤
V
CC
Output(s) disable
0V
≤
V
OUT
≤
V
CC
I
OH
= -4.0 mA
I
OL
= 8.0 mA
CONDITIONS
SYMBOL
V
IH
V
II
I
LI
I
LO
V
OH
V
OL
V
CC
3.0
MIN
2.2
-0.5
-10
-5
2.4
0.4
3.6
MAX
V
CC
+0.5
0.8
10
5
UNITS NOTES
V
V
µ
A
µ
A
V
V
V
1
1
1
1,2
1,2
DESCRIPTION
Power Supply
Current : Operating
TTL Standby
CMOS Standby
CONDITIONS
Device selected;
CE
≤
V
IL
; V
CC
=MAX;
f=f
MAX
; outputs open
CE
≥
V
IH
; V
CC
=MAX; f=f
MAX
CE1
≥
V
CC
-0.2; V
CC
= MAX;
SYMBOL
-10
I
CC
I
SB1
I
SB2
190
35
10
MAX
-12
160
30
10
-15
130
25
10
UNITS
mA
mA
mA
NOTES
3
all other inputs
≤
GND +0.2 or
≥
V
CC -
0.2;
all inputs static ; f=0
CAPACITANCE
DESCRIPTION
Input Capacitance
Input/Output Capacitance(DQ)
CONDITIONS
T
A
= 25°C ; f=1 MHz
V
CC
=3.3V
SYMBOL
C
I
C
I/O
MAX
6
8
UNITS NOTES
pF
pF
4
4
Elite Semiconduture Memory Technology Inc
Publication Date
:
Sep. 2000
Revision
:
1.0
3/14
$ %
AC ELECTRICAL CHARACTERISTICS
(Note 5)(All Temperature Ranges; V
CC
=3.3V
±
0.3V)
DESCRIPTION
Read Cycle
Read Cycle Time
Access access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Output Enable access time
Output Enable to output in Low-Z
Output Disable to output in High-Z
Byte Enable access time
Byte Enable to output in Low-Z
Byte disable to output in High-Z
Write Cycle
Write cycle time
Chip Enable to end of write
Address valid to end of write, with
OE
HIGH
Address setup time
Address hold from end of write
Write pulse width
Write pulse width, with
OE
HIGH
Data setup time
Data hold time
Write disable to output in Low-Z
Byte Enable to output in High-Z
Byte Enable to end of write
t
WC
t
CW
t
AW
t
AS
t
WR
t
WP2
t
WP1
t
DW
t
DH
t
OW
t
WHZ
t
BW
8
10
8
8
0
0
10
8
5
0
3
5
8
12
8
8
0
0
10
8
6
0
4
6
9
15
9
9
0
0
11
9
7
0
5
t
RC
t
AA
t
ACE
t
OH
t
CLZ
t
CHZ
t
OE
t
OLZ
t
OHZ
t
BE
t
BLZ
t
BHZ
0
5
0
5
6
0
6
3
3
5
5
0
6
7
0
10
10
10
4
4
6
6
0
12
12
12
4
4
15
SYMBOL
-10
MIN
MAX
MIN
-12
MAX
MIN
M21L216128A
-15
MAX
UNIT
Notes
ns
15
15
ns
ns
ns
ns
7
7
ns
ns
ns
7
8
ns
ns
ns
7
ns
4,7
4,6,7
4,6
4,7
4,6,7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
ns
ns
4,7
4,6,7
Elite Semiconduture Memory Technology Inc
Publication Date
:
Sep. 2000
Revision
:
1.0
4/14
$ %
TRUTH TABLE
MODE
LOW BYTE READ (DQ1-DQ8)
HIGH BYTE READ (DQ9-DQ16)
WORD READ (DQ1-DQ16)
LOW BYTE WRITE (DQ1-DQ8)
HIGH BYTE WRITE (DQ9-DQ16)
WORD WRITE (DQ1-DQ16)
CE
WE
OE
LE
HE
M21L216128A
DQ1-DQ8
Q
HIGH-Z
Q
D
HIGH-Z
D
HIGH-Z
HIGH-Z
HIGH-Z
DQ9-DQ16
HIGH-Z
Q
Q
HIGH-Z
D
D
HIGH-Z
HIGH-Z
HIGH-Z
POWER
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
STANBY
L
L
L
L
L
L
L
H
H
H
L
L
L
X
H
X
L
L
L
X
X
X
X
H
X
L
H
L
L
H
L
H
X
X
H
L
L
H
L
L
H
X
X
OUTPUT DISABLE
L
STANDBY
H
AC TEST CONDITIONS
Input plus levels
Input rise and fail times
Input timing reference levels
Output reference levels
Output load
0V to 3.0V
1.5ns
1.5V
1.5V
See Figures 1 and 2
3.3V
317
DQ
30pF
351
DQ
Z0 =50
è
50
Vt=1.5V
è
è
è
5pF
Fig.1 OUTPUT LOAD EQUIVALENT
Fig.2 OUTPUT LOAD EQUIVALENT
Elite Semiconduture Memory Technology Inc
Publication Date
:
Sep. 2000
Revision
:
1.0
5/14
FPGA/CPLD
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