UTRON
Rev. 1.0
256K X 16 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L25716(I) is a 4,194,304-bit low power
CMOS static random access memory organized as
262,144 words by 16 bits.
The UT62L25716(I) operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are
fully TTL compatible.
The UT62L25716(I) is designed for low power system
applications. It is particularly well suited for use in
high-density low power system applications.
UT62L25716(I)
FEATURES
High speed access time :
55ns(max) for Vcc=3.0V~3.6V
70/100 ns(max) for Vcc=2.7V~3.6V
CMOS Low power consumption
Operation current : 45/35/25 (Icc,max.)
Standby: 20uA (TYP.) L-version
3uA (TYP.) LL-version
Single 2.7V~3.6V power supply
Operation temperature:
Industrial : -40
℃
~85
℃
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage:1.5V (min.)
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 48-pin 6mm × 8mm TFBGA
PIN DESCRIPTION
SYMBOL
A0 - A17
I/O1 - I/O16
CE1
, CE2
WE
OE
LB
UB
Vcc
Vss
NC
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A8
A13
A14
A15
A16
A17
I/O1
I/O16
ROW
DECODER
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-Byte Control
High-Byte Control
Power Supply
Ground
No Connection
.
MEMORY ARRAY
VCC
VSS
.
.
2048 Rows x 128 Columns x 16 bits
PIN CONFIGURATION
.
.
.
A
COLUMN I/O
.
.
.
.
.
.
I/O
CONTROL
.
.
.
LB
I/O9
I/O10
OE
UB
I/O11
I/O12
I/O13
A0
A3
A5
A17
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE 1
CE2
B
C
D
E
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
NC
CE1
CE2
COLUMN DECODER
LOGIC
CONTROL
I/O2
I/O4
I/O5
I/O6
WE
OE
LB
Vss
Vcc
I/O15
I/O16
A12 A11 A10 A9 A7 A6 A5
F
G
H
UB
I/O14
NC
A8
WE
A11
NC
1
2
3
4
5
6
TFBGA
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80046
1
UTRON
Rev. 1.0
256K X 16 BIT LOW POWER CMOS SRAM
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.3 to 4.6
-40 to 85
-65 to 150
1.0~1.5
20
260.10
UNIT
V
℃
℃
W
mA
℃.sec
UT62L25716(I)
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Industrial
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
CE
1
H
X
X
L
L
L
L
L
L
L
L
Output
Disable
Read
Write
CE2
X
L
X
H
H
H
H
H
H
H
H
OE
X
X
X
H
H
L
L
L
X
X
X
WE
X
X
X
H
H
H
H
H
L
L
L
LB
X
X
H
L
X
L
H
L
L
H
L
UB
X
X
H
X
L
H
L
L
H
L
L
I/O1-I/O8
High – Z
High – Z
High – Z
High – Z
High – Z
D
OUT
High – Z
D
OUT
D
IN
High – Z
D
IN
I/O9-I/O16
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
D
OUT
D
OUT
High – Z
D
IN
D
IN
SUPPLY CURRENT
I
SB
, I
SB1
I
SB
, I
SB1
I
SB
, I
SB1
I
CC1
,I
CC2
I
CC1
,I
CC2
I
CC1
,I
CC2
Note:
H = V
IH
, L=V
IL
, X = Don't care.(Must be low or high state)
DC ELECTRICAL CHARACTERISTICS
(Vcc = 2.7V~3.6V, TA = -40
℃
to 85
℃
(I))
PARAMETER
SYMBOL
Power Voltage
Vcc
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Leakage Current
I
LI
Output Leakage Current
I
LO
Output High Voltage
V
OH
Output Low Voltage
V
OL
Operating Power
I
CC
Supply Current
Icc1
TEST CONDITION
MIN. TYP. MAX. UNIT
V
2.7
3.0
3.6
V
2.0
-
Vcc+0.3
V
- 0.2
-
0.6
µA
-1
-
1
µA
-1
-
1
V
2.2
-
-
V
-
-
0.4
55
-
mA
30
45
70
-
mA
25
35
mA
100 -
20
25
-
4
5
V
SS
≦
V
IN
≦
Vcc
V
SS
≦
V
I/O
≦
Vcc, Output Disabled
I
OH
= - 1.0mA
I
OL
= 2.1mA
Cycle time =min,100% duty, I
I/O
=0mA,
CE2=V
IH
,
CE1
=V
IL,
V
IN
=V
IH
or V
IL
,
Icc2
Standby Current
Standby Current
I
SB
I
SB1
Cycle time = 1us,100% duty, I
I/O
=0mA,
CE1
≦
0.2V, CE2
≧
Vcc-0.2V
other pins at 0.2V or Vcc-0.2V,
Cycle time =500ns,100% duty, I
I/O
=0mA,
CE1
≦
0.2V, CE2
≧
Vcc-0.2V
other pins at 0.2V or Vcc-0.2V,
CE1 =V
IH,
or CE2=V
IH
,other pins =V
IH
or V
IL
,
-L
CE1
≧
V
CC
-0.2V,or CE2
≦
0.2V,
-LL
other pins at 0.2V or Vcc-0.2V,
mA
-
8
10
mA
-
-
-
0.3
20
3
0.5
80
25
mA
µA
µA
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80046
2
UTRON
Rev. 1.0
256K X 16 BIT LOW POWER CMOS SRAM
UT62L25716(I)
CAPACITANCE
(TA=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 30pF, I
OH
/I
OL
= -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V~3.6V , TA = -40
℃
to 85
℃
(I))
(1) READ CYCLE
SYMBOL
UT62L25716(I)-55*
MIN.
MAX.
Read Cycle Time
t
RC
55
-
Address Access Time
t
AA
-
55
Chip Enable Access Time
t
ACE
-
55
Output Enable Access Time
t
OE
-
30
Chip Enable to Output in Low Z
t
CLZ*
10
-
Output Enable to Output in Low Z
t
OLZ*
5
-
Chip Disable to Output in High Z
t
CHZ*
-
20
Output Disable to Output in High Z
t
OHZ*
-
20
Output Hold from Address Change
t
OH
5
-
t
BA
-
55
LB
,
UB
Access Time
t
HZB
-
25
LB
,
UB
to High-Z Output
t
LZB
0
-
LB
,
UB
to Low-Z Output
(2) WRITE CYCLE
SYMBOL
UT62L25716(I)-55*
MIN.
MAX.
Write Cycle Time
t
WC
55
-
Address Valid to End of Write
t
AW
50
-
Chip Enable to End of Write
t
CW
50
-
Address Set-up Time
t
AS
0
-
Write Pulse Width
t
WP
45
-
Write Recovery Time
t
WR
0
-
Data to Write Time Overlap
t
DW
25
-
Data Hold from End of Write Time
t
DH
0
-
Output Active from End of Write
t
OW*
5
-
Write to Output in High Z
t
WHZ*
-
30
t
PWB
45
-
LB
,
UB
Valid to End of Write
PARAMETER
UT62L25716(I)-70
UT62L25716(I)-100
UNIT
PARAMETER
UT62L25716(I)-70
UT62L25716(I)-100
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
70
-
-
-
10
5
-
-
5
-
-
0
MAX.
-
70
70
35
-
-
25
25
-
70
30
-
MIN.
100
-
-
-
10
5
-
-
5
-
0
0
MAX.
-
100
100
50
-
-
30
30
-
100
40
-
MIN.
70
60
60
0
55
0
30
0
5
-
60
MAX.
-
-
-
-
-
-
-
-
-
30
-
MIN.
100
80
80
0
70
0
40
0
5
-
80
MAX.
-
-
-
-
-
-
-
-
-
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* These parameters are guaranteed by device characterization, but not production tested.
* 55ns for 3.0V~3.6V.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80046
3
UTRON
Rev. 1.0
256K X 16 BIT LOW POWER CMOS SRAM
UT62L25716(I)
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
t
AA
t
OH
t
OH
DOUT
Data Valid
READ CYCLE 2
(
CE1 and CE2
and
OE
Controlled)
(1,3,5,6)
t
RC
Address
t
AA
CE1
t
ACE1
CE2
t
ACE2
LB , UB
t
BLZ
OE
t
CLZ1
t
CLZ2
Dout
HIGH-Z
t
OE
t
OH
Data Valid
t
OHZ
t
CHZ1
t
CHZ2
HIGH-Z
t
OLZ
t
BHZ
Notes :
WE
is HIGH for read cycle.
2. Device is continuously selected CE1 =V
IL
and CE2=V
IH.
and
LB
=V
IL
and UB =V
IH.
1.
3. Address must be valid prior to or coincident with CE1 and CE2 and
LB
and UB transition; otherwise t
AA
is the limiting parameter.
4. OE is low.
5. t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
, t
CHZ2
and t
OHZ
are specified with C
L
=5pF. Transition is measured
±
500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ1
is less than t
CLZ1
, t
CHZ2
is less than t
CLZ2
, t
OHZ
is less than t
OLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80046
4
UTRON
Rev. 1.0
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5)
t
Address
t
CE1
t
CE2
t
CW1
CW2
AW
WC
256K X 16 BIT LOW POWER CMOS SRAM
UT62L25716(I)
t
WE
AS
t
t
WP
WR
LB , UB
t
Dout
Din
WH
t
PWB
t
High-Z
OW
(4)
t
DW
t
Data Valid
(4)
DH
WRITE CYCLE 2
(
CE1 and CE2
Controlled)
(1,2,5)
t
Address
WC
t
CE1
AW
t
AS
t
CW1
t
WR
t
CE2
CW2
WE
t
WP
LB , UB
t
t
WHZ
PWB
Dout
High-Z
t
Din
Notes :
1.
DW
t
Data Valid
DH
WE
or CE1 must be HIGH during all address transitions.
2. A write occurs during the overlap of a low CE1 and a low
WE
.
3. During a
WE
controlled with write cycle with OE LOW, t
WP
must be greater than t
WHZ
+t
DW
to allow the drivers to turn off and data to
be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the CE1 LOW transition occurs simultaneously with or after
WE
LOW transition, the outputs remain in a high impedance state.
6. t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured
±
500mV from steady state.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80046
5
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