Product Specification
PE43502
Product Description
The PE43502 is a HaRP™-enhanced, high linearity, 5-bit RF
Digital Step Attenuator (DSA). This highly versatile DSA
covers a 15.5 dB attenuation range in 0.5 dB steps. The
Peregrine 50Ω RF DSA provides multiple CMOS control
interfaces. It maintains high attenuation accuracy over
frequency and temperature and exhibits very low insertion loss
and low power consumption. Performance does not change
with V
DD
due to on-board regulator. This next generation
Peregrine DSA is available in a 4x4 mm 24-lead QFN footprint.
The PE43502 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
50
Ω
RF Digital Attenuator
5-bit, 15.5 dB, 9 kHz - 6 GHz
Features
•
HaRP™-enhanced UltraCMOS™ device
•
Attenuation: 0.5 dB steps to 15.5-dB
•
High Linearity: Typical +58 dBm IP3
•
Excellent low-frequency performance
•
3.3 V or 5.0 V Power Supply Voltage
•
Fast switch settling time
•
Programming Modes:
•
Direct Parallel
•
Latched Parallel
•
Serial
•
High-attenuation state @ power-up (PUP)
•
CMOS Compatible
•
No DC blocking capacitors required
•
Packaged in a 24-lead 4x4x0.85 mm QFN
Figure 1. Package Photo
24-lead 4x4x0.85 mm QFN Package
Figure 2. Functional Schematic Diagram
Switched Attenuator Array
RF Input
RF Output
Parallel Control
Serial In
CLK
LE
5
Control Logic Interface
P/S
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©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
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Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE43502
Product Specification
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.3 V or 5.0 V
Parameter
Frequency Range
Attenuation Range
Insertion Loss
Attenuation Error
Return Loss
Relative Phase
P1dB (note 1)
IIP3
Typical Spurious Value
Video Feed Through
Switching Time
RF Trise/Tfall
Settling Time
50% DC CTRL to 10% / 90% RF
10% / 90% RF
RF settled to within 0.05 dB of final value
RBW = 5 MHz, Averaging ON.
All States
Input
Two tones at +18 dBm, 20 MHz spacing
0 dB -
0 dB -
8 dB -
0 dB -
15.5 dB Attenuation settings
7.5 dB Attenuation settings
15.5 dB Attenuation settings
15.5 dB Attenuation settings
0.5 dB Step
9 kHz
≤
6 GHz
9 kHz < 4 GHz
4 GHz
≤
6 GHz
4 GHz
≤
6 GHz
4 GHz
≤
6 GHz
9 kHz - 6 GHz
9 kHz - 6 GHz
20 MHz - 6 GHz
20 MHz - 6 GHz
1 MHz
30
17
18
32
58
-110
10
650
400
4
Test Conditions
Frequency
Min
9 kHz
Typical
0 – 15.5
2.4
Max
6 GHz
Units
dB
2.9
±(0.3
+ 3%)
+0.4 + 4%
+0.6 + 8%
-0.2 - 3%
dB
dB
dB
dB
dB
dB
deg
dBm
dBm
dBm
mVpp
ns
ns
µs
Note 1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 3.
Performance Plots
Figure 3. 0.5dB Step Error vs. Frequency*
200MHz
900MHz
4000MHz
1800MHz
5000MHz
2200MHz
6000MHz
Figure 4. 1dB Attenuation vs. Attenuation State
Attenuation
35
30
900 MHz
2200 MHz
3800 MHz
5800 MHz
1.5
3000MHz
Attenuation
(dB)
dB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Step Error (dB)
25
20
15
10
5
0.5
0
-0.5
Attenuation Setting (dB)
0
0
5
10
15
20
25
30
35
*Monotonicity is held so long as Step-Error does not cross below -0.5
Attenuation State
Figure 5. 0.5dB Major State Bit Error
2
1.5
0.5 dB State
4dB State
1dB State
8dB State
2dB State
15.5dB State
Figure 6. 0.5dB Attenuation Error vs. Frequency
2
1.5
Attenuation Error (dB)
1
0.5
0
-0.5
-1
-1.5
-2
200MHz
3000MHz
900MHz
4000MHz
1800MHz
5000MHz
2200MHz
6000MHz
1
Bit Error (dB)
0.5
0
-0.5
-1
-1.5
-2
0
1000
2000
3000
Frequency (GHz)
4000
5000
6000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Attenuation Setting (dB)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
Document No. 70-0247-06
│
UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE43502
Product Specification
Figure 7. Insertion Loss vs. Temperature
-40C
0
-0.5
Insertion Loss (dB)
-1
-1.5
-2
-2.5
-3
-3.5
0
1
2
3
4
5
6
7
8
9
Frequency (GHz)
+25C
+85C
Figure 8. Input Return Loss vs. Attenuation
@ T = +25C
0
-5
Input Return Loss (dB)
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
6
7
8
9
Frequency (GHz)
0dB
4dB
0.5dB
8dB
1dB
15.5dB
2dB
Figure 9. Output Return Loss vs. Attenuation
@ T = +25C
0
-5
-10
Return Loss (dB)
-15
-20
-25
-30
-35
-40
-45
0
1
2
3
4
5
6
7
8
9
Frequency (GHz)
0dB
4dB
0.5dB
8dB
1dB
15.5dB
2dB
Figure 10. Relative Phase vs. Frequency
35
30
Relative Phase Error (Deg)
25
20
15
10
5
0
0
1
2
3
4
Frequency (GHz)
5
6
7
8
0dB
4dB
0.5dB
8dB
1dB
15.5dB
2dB
Figure 11. Attenuation Error vs. Temperature
@ 6 GHz
2
1.5
Attenuation Error (dB)
1
0.5
0
-0.5
-1
-1.5
-2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Attenuation Setting (dB)
-40C
+25C
+85C
Figure 12. Input IP3 vs. Frequency
0dB
0.5dB
1dB
2dB
4dB
8dB
70
65
60
Input IP3 (dBm)
55
50
45
40
35
30
0
500
1000
1500
2000
2500
3000
3500
4000
4500
Frequency (MHz)
Document No. 70-0247-06
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©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE43502
Product Specification
Figure 13. Pin Configuration (Top View)
C 0.5
GND
C1
C2
C4
C8
24
23
22
21
20
19
Table 3. Operating Ranges
Parameter
V
DD
Power Supply Voltage
Min
3.0
Typ
3.3
5.0
70
2.6
5.5
350
5.5
Fig. 14
+23
-40
0
25
85
1
15
Max
Units
V
V
µA
V
dBm
dBm
°C
V
µA
GND
VDD
P/S
GND
RF1
GND
1
2
3
4
5
6
10
11
12
7
8
9
18
17
16
15
14
13
SI
CLK
LE
GND
RF2
GND
V
DD
Power Supply Voltage
I
DD
Power Supply Current
Digital Input High
P
IN
Input power (50Ω):
9 kHz
≤
20 MHz
20 MHz
≤
6 GHz
T
OP
Operating temperature range
Digital Input Low
Exposed
Solder
Pad
GND
GND
GND
GND
GND
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
6 - 13
14
15
16
17
18
19
20
21
22
23
24
Paddle
GND
Digital Input Leakage
1
Pin Name
GND
V
DD
P̅
/S
GND
RF1
GND
RF2
GND
LE
CLK
SI
GND
C8 (D5)
C4 (D4)
C2 (D3)
C1 (D2)
C0.5 (D1)
GND
Ground
Description
Power supply pin
Serial/Parallel mode select
Ground
RF1 port
Ground
RF2 port
Ground
Serial interface Latch Enable input
Serial interface Clock input
Serial interface Data input
Ground
Parallel control bit, 8 dB
Parallel control bit, 4 dB
Parallel control bit, 2 dB
Parallel control bit, 1 dB
Parallel control bit, 0.5 dB
Ground for proper operation
Note 1. Input leakage current per Control pin
Table 4. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
P
IN
V
ESD
Parameter/Conditions
Power supply voltage
Voltage on any Digital input
Storage temperature range
Input power (50Ω)
9 kHz
≤
20 MHz
20 MHz
≤
6 GHz
ESD voltage (HBM)
1
ESD voltage (Machine Model)
Min
-0.3
-0.3
-65
Max
6.0
5.8
150
Fig. 14
+23
500
100
Units
V
V
°C
dBm
dBm
V
V
Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Figure 14. Maximum Power Handling Capability
30
25
Note: Ground C0.5, C1 C2, C4, C8, if not in use.
Exposed Solder Pad Connection
Pin dBm
20
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
15
10
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE43502 in
the 24-lead 4x4 QFN package is MSL1.
5
0
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Hz
1.0E+07
1.0E+08
1.0E+09
Switching Frequency
The PE43503 has a maximum 25 kHz switching rate.
Switching rate is defined to be the speed at which the
DSA can be toggled across attenuation states.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
Document No. 70-0247-06
│
UltraCMOS™ RFIC Solutions
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE43502
Product Specification
Table 5. Control Voltage
State
Low
High
Table 8. Attenuation Word Truth Table
Bias Condition
Attenuation Word
D7
D6
L
L
L
L
L
L
L
0 to +1.0 Vdc at 2
µA
(typ)
D5
L
L
L
L
L
H
H
D4
L
L
L
L
H
L
H
D3
L
L
L
H
L
L
H
D2
L
L
H
L
L
L
H
D1
L
H
L
L
L
L
H
+2.6 to +5 Vdc at 10
µA
(typ)
L
L
D0
(LSB)
L
L
L
L
L
L
L
Attenuation
Setting
RF1-RF2
Reference I.L.
0.5 dB
1 dB
2 dB
4 dB
8 dB
15.5 dB
Table 6. Latch and Clock Specifications
Latch Enable
X
↑
L
L
L
L
L
Shift Clock
↑
X
Function
Shift Register Clocked
Contents of shift register
transferred to attenuator core
Table 7. Parallel Truth Table
Parallel Control Setting
D5
L
L
L
L
L
H
H
D4
L
L
L
L
H
L
H
D3
L
L
L
H
L
L
H
D2
L
L
H
L
L
L
H
D1
L
H
L
L
L
L
H
Attenuation Setting
RF1-RF2
Reference I.L.
0.5 dB
1 dB
2 dB
4 dB
8 dB
15.5 dB
Table 9. Serial Register Map
MSB (last in)
Q7
D7
Q6
D6
Q5
D5
Q4
D4
Q3
D3
Q2
D2
LSB (first in)
Q1
D1
Q0
D0
Bits must be set to logic low
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 12.5 dB state:
Attenuation Word: Multiply by 4 and convert to binary
→
4 * 12.5 dB
→
50
→
00110010
Serial Input: 00110010
Document No. 70-0247-06
│
www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
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Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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