UTRON
Rev. 1.1
REVISION HISTORY
REVISION
DESCRIPTION
REV. 0.9
Original.
REV. 1.0 1. The symbols CE1# ,OE# & WE# are revised as CE , OE &
WE
.
2. I
cc1
is revise as I
cc
.
3. I
cc2
is revise as I
cc1
.
REV. 1.1 Add order information for lead free product
UT62W1024
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
DATE
Mar.15. 2001
Jul. 06. 2001
May. 16. 2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80056
1
UTRON
Rev. 1.1
UT62W1024
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62W1024 is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT62W1024 is designed for low power
application. It is particularly well suited for battery
back-up nonvolatile memory application.
The UT62W1024 operates from a wide range of
2.7V~ 5.5V power supply and all inputs and outputs
are fully TTL compatible.
FEATURES
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 60/50/40 mA (typical)
Standby : 10µA (typical) L-version
1µA (typical) LL-version
Wide range power supply : 2.7V to 5.5V
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8x20mm TSOP-1
32-pin 8x13.4mm STSOP
PIN CONFIGURATION
NC
A16
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
FUNCTIONAL BLOCK DIAGRAM
1024 X 1024
MEMORY
ARRAY
A12
A7
A6
A5
A0-A16
DECODER
A13
A8
A9
A11
OE
UT62W1024
Vcc
Vss
A4
A3
A2
A1
A0
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
I/O1
I/O2
I/O3
Vss
PDIP / SOP
CE
CE2
OE
W
E
CONTROL
CIRCUIT
A11
A9
A8
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A3
WE
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O1 - I/O8
CE ,CE2
WE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip enable 1,2 Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
UT62W1024
25
24
23
22
21
20
19
18
17
TSOP-I/STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80056
2
UTRON
Rev. 1.1
UT62W1024
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to Vss
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
T
solder
RATING
-0.5 to +4.6
0 to +70
-65 to +150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Standby
Output Disable
Read
Write
CE
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION
High - Z
High -Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
,
I
SB1
I
SB
,
I
SB1
I
CC
I
CC
I
CC
Note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS (
Ⅰ
)
(V
CC
= 2.7V~3.6V, Vss=0V, T
A
= 0
℃
to 70
℃
)
PARAMETER
SYMBOL TEST CONDITION
*1
Input High Voltage
V
IH
*2
Input Low Voltage
V
IL
Input Leakage Current
I
IL
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current I
OL
V
SS
≦
V
I/O
≦
V
CC
CE =V
IH
or CE2=V
IL
or
Output High Voltage
Output Low Voltage
Average Operating
Power Supply Courrent
V
OH
V
OL
I
CC
OE
=V
IH
or
WE
=V
IL
I
OH
= -1mA
I
OL
= 4mA
Cycle time =Min. 100% Duty,
CE =V
IL
, CE2 = V
IH
,
I
I/O
= 0mA
Cycle time = 1µs, 100% Duty,
CE
≦
0.2V,CE2
≧
V
CC
-0.2V,
C
L
=50PF
CE =V
IH
or CE2 = V
IL
CE
≧
V
CC
-0.2V or
CE2
≦
0.2V
-L
-
LL
MIN.
2.0
- 0.5
-1
-1
2.2
-
-
-
-
-
-
-
-
TYP.
MAX.
-
V
CC
+0.5
-
0.6
-
1
-
-
-
40
35
30
-
-
2.5
0.5
1
-
0.4
60
50
40
5
1.0
100
*4
20
40
*4
10
UNIT
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
µA
µA
-35
-55
-70
I
CC1
Standby Power
Supply Current
I
SB
I
SB1
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
4. Those parameters are for reference only under 50
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80056
3
UTRON
Rev. 1.1
UT62W1024
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS (
Ⅱ
)
(V
CC
= 4.5V~5.5V, Vss=0V, TA = 0
℃
to 70
℃
)
PARAMETER
SYMBOL TEST CONDITION
*1
Input High Voltage
V
IH
*2
Input Low Voltage
V
IL
Input Leakage Current
I
IL
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current I
OL
V
SS
≦
V
I/O
≦
V
CC
CE =V
IH
or CE2=V
IL
or
Output High Voltage
Output Low Voltage
Average Operating
Power Supply Courrent
V
OH
V
OL
I
CC
OE
=V
IH
or
WE
=V
IL
I
OH
=-1mA
I
OL
= 4mA
Cycle time =Min. 100% Duty,
CE =V
IL
, CE2 = V
IH
,
C
L
=100PF
Cycle time = 1µs, 100% Duty,
CE
≦
0.2V,CE2
≧
V
CC
-0.2V,
I
I/O
= 0mA
CE =V
IH
or CE2 = V
IL
CE
≧
V
CC
-0.2V or
CE2
≦
0.2V
-L
-
LL
MIN.
2.2
- 0.5
-1
-1
2.4
-
-
-
-
-
-
-
-
TYP.
-
-
-
-
-
-
60
50
-40
-
-
2.5
0.5
MAX.
V
CC
+0.5
0.8
1
1
-
0.4
100
85
70
5
1.0
100
*3
20
40
*3
10
UNIT
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
µA
µA
-35
-55
-70
I
CC1
Standby Power
Supply Current
I
SB
I
SB1
*1. V
IH
(max)=Vcc+3.0v for pulse width less than 10ns.
*2. V
IL
(min)=Vss-3.0v for pulse width less than 10ns.
*3. Those parameters are for reference only under 50℃
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80056
4
UTRON
Rev. 1.1
UT62W1024
128K X 8 BIT WIDE RANGE LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX.
8
10
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
=100pF, I
OH
/I
OL
=-1mA/4mA(V
CC
=5V)
C
L
=50pF, I
OH
/I
OL
=-1mA/2mA(V
CC
=3.3V)
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~5.5V, V
SS
=0V , T
A
= 0
℃
to 70
℃
)
(1) READ CYCLE
PARAMETER
SYMBOL
UT62W1024-35 UT62W1024-55 UT62W1024-70
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
35
-
55
-
70
-
Address Access Time
t
AA
-
35
-
55
-
70
Chip Enable Access Time
t
ACE
-
35
-
55
-
70
Output Enable Access Time
t
OE
-
25
-
30
-
35
Chip Enable to Output in Low-Z
t
CLZ
*
10
-
10
-
10
-
Output Enable to Output in Low-Z t
OLZ
*
5
-
5
-
5
-
Chip Disable to Output in High-Z
t
CHZ
*
-
25
-
30
-
35
Output Disable to Output in High-Z t
OHZ
*
-
25
-
30
-
35
Output Hold from Address Change t
OH
5
-
5
-
5
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write-Time
Output Active from End of Write
Write to Output in High-Z
SYMBOL
UT62W1024-35 UT62W1024-55
MIN.
MAX. MIN. MAX.
t
WC
35
-
55
-
t
AW
30
-
50
-
t
CW
30
-
50
-
t
AS
0
-
0
-
t
WP
25
-
40
-
t
WR
0
-
0
-
t
DW
20
-
25
-
t
DH
0
-
0
-
t
OW
*
5
-
5
-
t
WHZ
*
-
15
-
20
UT62W1024-70
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
70
60
60
0
45
0
30
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
25
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80056
5
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