ESMT
DDR SDRAM
Features
M13S5121632A (2S)
8M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Double-data-rate architecture, two data transfers per clock cycle
Bi-directional data strobe (DQS)
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Four bank operation
CAS Latency : 2.5, 3, 4
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock (CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
Data mask (DM) for write masking only
V
DD
= 2.5V
±
0.2V, V
DDQ
= 2.5V
±
0.2V
7.8us refresh interval
Auto & Self refresh
2.5V I/O (SSTL_2 compatible)
Ordering Information
Product ID
M13S5121632A -5TG2S
M13S5121632A -6TG2S
Max Freq.
200MHz (DDR400)
166MHz (DDR333)
V
DD
2.5V
Package
66 pin TSOPII
Comments
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
1/48
ESMT
Functional Block Diagram
CLK
CLK
CKE
Address, BA
Mode Register &
Extended Mode
Register
Clock
Generator
M13S5121632A (2S)
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
DQS
Sense Amplifier
DM
Command Decoder
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
RAS
Control Logic
CS
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
DQ
CLK, CLK
DLL
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
2/48
ESMT
PIN CONFIGURATION (TOP VIEW)
(TSOPII 66L, 400milX875mil Body, 0.65mm Pin Pitch)
M13S5121632A (2S)
Pin Description
Pin Name
Function
Address inputs
- Row address A0~A12
- Column address A0~A9
A10/AP: AUTO Precharge
BA0, BA1: Bank selects (4 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Pin Name
Function
DM is an input mask signal for write data.
LDM corresponds to the data on DQ0~DQ7;
UDM correspond to the data on DQ8~DQ15.
Clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
Reference Voltage for SSTL_2
No connection
A0~A12,
BA0, BA1
LDM, UDM
DQ0~DQ15
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
V
REF
NC
V
SS
V
DD
Bi-directional Data Strobe.
LDQS, UDQS LDQS corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on DQ8~DQ15.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
3/48
ESMT
Absolute Maximum Rating
Parameter
Voltage on V
DD
& V
DDQ
supply relative to V
SS
Voltage on inputs relative to V
SS
Voltage on I/O pins relative to V
SS
Operating ambient temperature
Storage temperature
Power dissipation
Short circuit current
Note:
Symbol
V
DD
, V
DDQ
V
INPUT
V
IO
T
A
T
STG
P
D
I
OS
M13S5121632A (2S)
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ V
DDQ
+0.5
0 ~ +70
-55 ~ +150
1
50
Unit
V
V
V
°C
°C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Conditions & Specifications
DC Operation Conditions
Recommended operating conditions (Voltage reference to V
SS
= 0V)
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
V–I Matching: Pullup to Pulldown Current Ratio
Input leakage current: Any input 0V
V
IN
V
DD
(All other pins not tested under = 0V)
Output leakage current
(DQs are disable; 0V
V
OUT
V
DDQ
)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
VI (Ratio)
I
L
I
OZ
Min
2.3
2.3
0.49*V
DDQ
V
REF
- 0.04
V
REF
+ 0.15
-0.3
-0.3
0.36
0.71
-2
-5
Max
2.7
2.7
0.51*V
DDQ
V
REF
+ 0.04
V
DDQ
+ 0.3
V
REF
- 0.15
V
DDQ
+ 0.3
V
DDQ
+ 0.6
1.4
2
5
Unit
V
V
V
V
V
V
V
V
-
3
4
1
2
Note
A
A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
4/48
ESMT
DC Operation Conditions - continued
Parameter
Output High Current (Full strength driver – Normal)
(V
OUT
=V
DDQ
-0.373V, min V
REF
, min V
TT
)
Output Low Current (Full strength driver – Normal)
(V
OUT
= 0.373V, max V
REF
, max V
TT
)
Output High Current (Reduced strength driver –Weak)
(V
OUT
= V
DDQ
-0.763V, min V
REF
, min V
TT
)
Output Low Current (Reduced strength driver – Weak)
(V
OUT
= 0.763V, max V
REF
, max V
TT
)
Output High Current (Reduced strength driver –
Matched impedance)
(V
OUT
= V
DDQ
-1.056V, min V
REF
, min V
TT
)
Output Low Current (Reduced strength driver –
Matched impedance)
(V
OUT
= 1.056V, max V
REF
, max V
TT
)
Symbol
I
OH
I
OL
I
OH
I
OL
Min
-15
+15
-9
+9
M13S5121632A (2S)
Max
Unit
mA
mA
mA
mA
Note
5, 7
5, 7
6
6
I
OH
-4.5
mA
6
I
OL
+4.5
mA
6
Notes:
1. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
2. V
TT
is not applied directly to the device. V
TT
is system supply for signal termination resistors, is expected to be set
equal to V
REF
, and must track variations in the DC level of V
REF
.
3. V
ID
is the magnitude of the difference between the input level on CLK and the input level on CLK .
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25 V to 1.0 V. For a given output, it represents
the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
5. V
OH
= 1.95V, V
OL
=0.35V.
6. V
OH
= 1.9V, V
OL
=0.4V.
7. The values of I
OH
(DC) is based on V
DDQ
= 2.3V and V
TT
= 1.19V.
The values of I
OL
(DC) is based on V
DDQ
= 2.3V and V
TT
= 1.11V.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
5/48
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