ESMT
Flash
FEATURES
Voltage Supply: 2.6V ~ 3.6V
Organization
- Memory Cell Array: (128M + 4M) x 8bit
- Data Register: (2K + 64) x 8bit
Automatic Program and Erase
- Page Program: (2K + 64) bytes
- Block Erase: (128K + 4K) bytes
Page Read Operation
- Page Size: (2K + 64) bytes
- Random Read: 25us (Max.)
- Serial Access: 25ns (Min.)
Memory Cell: 1bit/Memory Cell
Fast Write Cycle Time
- Program time: 200us (Typ.)
- Block Erase time: 1.5ms (Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating Gate Technology
Endurance:
- 100K Program/Erase Cycles (with 1 bit/528 bytes ECC)
- Data Retention: 10 Years
Command Driven Operation
Cache Program Operation for High Performance Program
Copy-Back Operation
No Bad-Block-Erasing-Protect function (user should manage
bad blocks before erasing)
F59L1G81A
1 Gbit (128M x 8)
3.3V NAND Flash Memory
ORDERING INFORMATION
Product ID
F59L1G81A -25TG
F59L1G81A -25BG
Speed
25 ns
25 ns
Package
48 pin TSOPI
63 ball BGA
Comments
Pb-free
Pb-free
GENERAL DESCRIPTION
Offered in 128Mx8 bits, this device is 1Gbit with spare 32Mbit
capacity. The device is offered in 3.3V V
CC
. Its NAND cell
provides the most cost effective solution for the solid state mass
storage market. A program operation can be performed in typical
200us on the 2,112-byte page and an erase operation can be
performed in typical 1.5ms on a (128K+4K) bytes block. Data in
the data register can be read out at 25ns cycle time per byte.
The I/O pins serve as the ports for address and data input/output
as well as command input. The on-chip write controller
automates all program and erase functions including pulse
repetition, where required, and internal verification and
margining of data. Even the write-intensive systems can take
advantage of this device’s extended reliability of 100K
program/erase cycles by providing ECC (Error Correcting Code)
with real time mapping-out algorithm.
This device is an optimum solution for large nonvolatile storage
applications such as solid state file storage and other portable
applications requiring non-volatility.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2013
Revision: 1.2
1/35
ESMT
PIN CONFIGURATION (TOP VIEW)
(TSOPI 48L, 12mm X 20mm Body, 0.5mm Pin Pitch)
NC
NC
NC
NC
NC
NC
R/B
RE
CE
NC
NC
V
CC
V
SS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
F59L1G81A
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
V
CC
V
SS
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
BALL CONFIGURATION (TOP VIEW)
(
BGA 63 BALL , 9mm X 11mm Body , 0.8 Ball Pitch
)
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
G
H
J
K
L
M
NC
NC
NC
NC
NC
NC
NC
WP
ALE
V
SS
CE
WE
R/B
NC
RE
CLE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
CC
NC
I/O0
NC
NC
NC
NC
I/O1
NC
V
CC
I/O5
I/O7
V
SS
I/O2
I/O3
I/O4
I/O6
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2013
Revision: 1.2
2/35
ESMT
Pin Description
Symbol
I/O0~I/O7
Pin Name
Data Inputs / Outputs
Functions
F59L1G81A
The I/O pins are used to input command, address and data, and to output data
during read operations. The I/O pins float to Hi-Z when the chip is deselected
or when the outputs are disabled.
The CLE input controls the activating path for commands sent to the command
register. When active high, commands are latched into the command register
through the I/O ports on the rising edge of the
WE
signal.
The ALE input controls the activating path for address to the internal address
registers. Addresses are latched on the rising edge of
WE
with ALE high.
The CE input is the device selection control. When the device is in the Busy
state, CE high is ignored, and the device does not return to standby mode.
The
RE
input is the serial data-out control, and when active drives the data
CLE
Command Latch
Enable
Address Latch Enable
ALE
CE
Chip Enable
RE
Read Enable
onto the I/O bus. Data is valid t
REA
after the falling edge of
RE
which also
increments the internal column address counter by one.
The
WE
input controls writes to the I/O port. Commands, address and data
are latched on the rising edge of the
WE
pulse.
The
WP
pin provides inadvertent program/erase protection during power
WE
Write Enable
WP
Write Protect
transitions. The internal high voltage generator is reset when the
WP
pin is
active low.
The R/
B
output indicates the status of the device operation. When low, it
indicates that a program, erase or random read operation is in process and
returns to high state upon completion. It is an open drain output and does not
float to Hi-Z condition when the chip is deselected or when outputs are
disabled.
V
CC
is the power supply for device.
Lead is not internally connected.
R /B
Ready / Busy Output
V
CC
V
SS
NC
Power
Ground
No Connection
Note:
Connect all V
CC
and V
SS
pins of each device to common power supply outputs. Do not leave V
CC
or V
SS
disconnected.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2013
Revision: 1.2
3/35
ESMT
BLOCK DIAGRAM
F59L1G81A
ARRAY ORGANIZATION
Address Cycle Map
I/O0
1st cycle
2nd cycle
3rd cycle
4th cycle
A0
A8
A12
A20
I/O1
A1
A9
A13
A21
I/O2
A2
A10
A14
A22
I/O3
A3
A11
A15
A23
I/O4
A4
L*
A16
A24
I/O5
A5
L*
A17
A25
I/O6
A6
L*
A18
A26
I/O7
A7
L*
A19
A27
Column Address
Column Address
Row Address
(Page Address)
Note:
1. Column Address: Starting Address of the Register.
2. *L must be set to “Low”.
3. * The device ignores any additional input of address cycles than required.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2013
Revision: 1.2
4/35
ESMT
Product Introduction
F59L1G81A
This device is a 1,056Mbits (1,107,296,256 bits) memory organized as 65,539 rows (pages) by 2,112-byte columns. Spare 64-byte
columns are located from column address of 2,048 to 2,111.
A 2,112-byte data register and 2,112-byte cache register are serially connected to each other. Those serially connected registers are
connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and
page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the
32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total
1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is
executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte blocks. It indicates that the bit by bit
erase operation is prohibited on the device.
This device uses addresses multiplexed scheme. This scheme dramatically reduces pin counts and allows systems upgrades to future
densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing
WE
to low while CE is low. Those are latched on the rising edge of
WE
. Command Latch Enable (CLE) and Address Latch
Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The total physical space requires 28
addresses, thereby requiring four cycles for addressing: 2 cycle of column address, 2 cycles of row address, in that order. Page Read
and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only
the 2 cycles of row address are used. Device operations are selected by writing specific commands into the command register. Below
table defines the specific commands of this device.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers are
being programmed into memory cells in cache program mode. The program performance may be dramatically improved by cache
program when there are lots of pages of data to be programmed.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Command Set
Function
Read
Read for Copy Back
Read ID
Reset
Page Program
Cache Program
Copy-Back Program
Block Erase
Random Data Input
(1)
Random Data Output
(1)
Read Status
1st Cycle
00h
00h
90h
FFh
80h
80h
85h
60h
85h
05h
70h
2nd Cycle
30h
35h
-
-
10h
15h
10h
D0h
-
E0h
-
Acceptable Command
during Busy
O
O
Note:
1. Random Data Input / Output can be executed in a page.
Caution:
Any undefined command inputs are prohibited except for above command set of above table.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2013
Revision: 1.2
5/35
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