上海双岭电子有限公司是上海市高新技术企业,是国内研制和生产场效应半导体器件最早的专业化企业,在航空、通讯、传感、仪器仪表和自动化控制等领域有广泛的市场。
公司主要产品有二极管、结型场效应晶体管、MOS型场效应晶体管和CC4000系列CMOS集成电路。“双岭牌三大系列产品均已通过国军标GJB9001A-2001质量管理体系认证”,以可靠的质量和完善的服务赢得新老顾客的信赖和赞誉。
公司采用CAD计算机辅助设计系统及线宽1.2um的制作工艺,可助您将线路集成化、专用化的设想成为现实,使您的产品更具有市场竞争力。
"双岭" 致力诚信商誉,打造精良品牌"一直是双岭人的追求。
ASYNCHRONOUS PARALLELIN ORSYNCHRONOUS SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER 异步并行或同步8/串行串行输出 - 第一阶段静态移位寄存器
功能特点
产品名称:ASYNCHRONOUS PARALLELIN ORSYNCHRONOUS SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER 异步并行或同步8/串行串行输出 - 第一阶段静态移位寄存器
产品型号:CC4021
产品特征:
1. MEDIUM SPEED OPERATION:
12 MHz (Typ.) CLOCK RATE AT VDD - VSS = 10V
2. FULLY STATIC OPERATION
3. 8 MASTER-SLAVE FLIP-FLOPS PLUS OUTPUT BUFFERING AND CONTROL
GATING
4. QUIESCENT CURRENT SPECIFIED UP TO 20V
5. 5V, 10V AND 15V PARAMETRIC RATINGS
6. INPUT LEAKAGE CURRENT:
II = 100nA (MAX) AT VDD = 18V TA = 25?C
7. 100% TESTEDFOR QUIESCENT CURRENT
8. MEETS ALL REQUIREMENTS OF JEDEC JESD13B ” STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES”
产品描述:
1. The CC4021 is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages.
2. This device is an 8-stage parallel or serial input/serial output register having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel ”JAM” inputs to each register stage. Each register stage is a D-type, master-slave flip-flop in addition to an output from stage 8, ”Q” outputs are also available
from stages 6 and 7. Serial entry is synchronous with the clock but parallel entry is asynchronous. In this device, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of he clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line, the CLOCK input of the internal stage is ”forced” when asynchronous parallel entry is made. Register expansion using multiple package is permitted.
产品封装:DIP
热搜元器件
电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved