SH66L08A
1K 4-bit Micro-controller with LCD Driver
Features
SH6610C-based single-chip 4-bit micro-controller with
LCD driver
ROM: 1024 X 16 bits
RAM: 288 X 4 bits
- 32 System Control Register
- 256 Data memory
- 34 LCD RAM
Operation Voltage: 1.2V - 1.7V
16 CMOS Bi-directional I/O pads (PORTC, PORTD can
switch to LCD segment)
4-Level Stack (Including Interrupts)
Two 8-bit Auto Re-Loaded Timers/Counters
Warm-Up Timer
Powerful Interrupt Sources:
- External interrupt (Low active)
- Timer0 interrupt
- Timer1 interrupt
- PORTB & PORTC interrupt (Low active)
Oscillator (Code Option)
- Crystal Oscillator:
32.768kHz
- RC Oscillator:
131kHz
Instruction Cycle Time (4/f
OSC
)
LCD Driver:
- 34SEG X 4COM (1/4 Duty, 1/3 Bias)
- 34SEG X 3COM (1/3 Duty, 1/2 Bias)
Two Low Power Operation Modes: HALT And STOP
Built-in Watchdog Timer (Code Option)
Built-in Voltage Doubler And Tripler Charge Pump
Circuit
Built-in Alarm Generator
Low power consumption
Bonding option for multi-code software
Available in CHIP FORM
General Description
SH66L08A is a single-chip 4-bit micro-controller. This device integrates a SH6610C CPU core, SRAM, timer, alarm generator,
LCD driver, I/O port, voltage pump and program ROM. The SH66L08A is suitable for calculator application.
Pad Configuration
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
46
SEG13
45
44
43
42
41
40
39
SEG25
SEG26
PORTC0/SEG27
PORTC1/SEG28
PORTC2/SEG29
PORTC3/SEG30
PORTD0/SEG31
PORTD1/SEG32
PORTD2/SEG33
PORTD3/SEG34
PORTA0
PORTA1
PORTA2
PORTA3
PORTB0
PORTB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
56
55
54
53
52
51
50
49
48
47
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM4
COM3
COM2
COM1
SH66L08A
38
37
36
35
34
33
32
31
17
18
19
B0
20
21
22
B1
30
23
24
25
26
27
28
29
RESET
OSCI
PORTB2
PORTB3
GND
VDD
CUP1
OSCO
1
CUP2
TEST
VP2
VP1
V2.0
SH66L08A
Pad Description (
Total 58 pads for mask type)
Pad No.
33 - 56,1 - 2
29 - 32
28, 27
25, 26
24
23
19
Designation
SEG1 - 26
COM1 - 4
VP1, VP2
CUP1 - 2
TEST
I/O
O
O
P
P
I
I
P
I
I
P
O
I
I/O
I/O
I/O
I/O
Description
Segment signal output for LCD display
Common signal output for LCD display
Power supply pad for LCD driver
Connection for voltage doubler capacitor
Test pad internally pull-down. (No connect for user)
Pad reset input
Power supply pad
Bonding option (Internally pull-low)
Bonding option (Internally pull-high)
Ground pad
OSC output pad. No output in RC mode.
OSC input pad, connected to a crystal or external resistor.
Bit programmable I/O, PORTA.0 could be external interrupt input (
INT
)
PORTA.1, PORTA.2 could be buzzer output PORTA.1 (BD), PORTA.2 (
BD
)
Bit programmable I/O, vector interrupt (Active low level)
Bit programmable I/O, Vector interrupt (Active low level)
Shared with SEG27 - 30
Bit programmable I/O. shared with SEG31 - 34
Z: High impedance
RESET
V
DD
B0
B1
22
20
21
11 - 14
15 - 18
3-6
7 - 10
Which, I: input;
GND
OSCO
OSCI
PORTA.0 - 3
PORTB.0 - 3
PORTC.0 - 3
PORTD.0 - 3
O: output;
P: Power;
3
SH66L08A
Functional Description
1. CPU
The CPU contains the following functional blocks: Program
Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY),
Accumulator, Table Branch Register, Data Pointer (INX, DPH,
DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can address only 4K program ROM.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, ADCM, ADD, ADDM,
SBC, SBCM, SUB, SUBM, ADI, ADIM, SBI, SBIM)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, ANDM, EOR, EORM, OR, ORM,
ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service or
CALL instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register, or
data memory can be performed.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep data
after the CPU entering STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register and I/O: $000 - $01F
Data memory $020 - $11F
LCD RAM space: $300 - $321: (34 X 4 bits)
RAM bank table:
Bank0
B=0
$020 - $07F
Bank1
B=1
$080 - $0FF
Bank2
B=2
$100 - $17F
Bank6
B=6
$300 - $3FF
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are placed
by an offset address in program ROM. TJMP instruction
8
branch into address ((PC11 - PC8) X (2 ) + (TBR, AC)). The
address is determined by RTNW to return look-up value into
(TBR, AC). ROM code Bit7 - Bit4 is placed into TBR and
Bit3-Bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bit), DPM (3-bit)
and DPL (4-bit). The addressing range is 000H-3FFH.
Pseudo index address (INX) is used to read or write Data
memory, then RAM address Bit9 - Bit0 which comes from
DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents of
CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into 13
bits X 4 levels. The stack is operated on a first-in, last-out
basis and returned sequentially to the PC by the return
instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 4 levels. If the number of calls and
interrupt requests exceeds 4, then the bottom of stack will be
shifted out, that program execution may enter an abnormal
state.
Where, B: RAM bank bit use in instructions
4
SH66L08A
2.2. Configuration of System Register
Address
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16 - $19
$1A
$1B
$1C
$1D
$1E
$1F
Bit 3
IEX
IRQX
-
-
T0L.3
T0H.3
T1L.3
T1H.3
PA.3
PB.3
PC.3
PD.3
-
-
TBR.3
INX.3
DPL.3
-
-
-
AEC3
PPULL
-
WDT
PACR.3
PBCR.3
PCCR.3
PDCR.3
-
Bit 2
IET0
IRQT0
T0M.2
T1M.2
T0L.2
T0H.2
T1L.2
T1H.2
PA.2
PB.2
PC.2
PD.2
-
-
TBR.2
INX.2
DPL.2
DPM.2
DPH.2
LCDOFF
AEC2
O/S2
-
-
PACR.2
PBCR.2
PCCR.2
PDCR.2
-
Bit 1
IET1
IRQT1
T0M.1
T1M.1
T0L.1
T0H.1
T1L.1
T1H.1
PA.1
PB.1
PC.1
PD.1
-
B1
TBR.1
INX.1
DPL.1
DPM.1
DPH.1
HLM
AEC1
O/S1
-
-
PACR.1
PBCR.1
PCCR.1
PDCR.1
-
Bit 0
IEP
IRQP
T0M.0
T1M.0
T0L.0
T0H.0
T1L.0
T1H.0
PA.0
PB.0
PC.0
PD.0
-
B0
TBR.0
INX.0
DPL.0
DPM.0
DPH.0
PAM
AEC0
-
-
-
PACR.0
PBCR.0
PCCR.0
PDCR.0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
-
Remarks
Interrupt enable flags register
Interrupt request flags register
Bit2-0: Timer0 Mode register
Bit2-0: Timer1 Mode register
Timer0 load/counter register low nibble register
Timer0 load/counter register high nibble register
Timer1 load/counter register low nibble register
Timer1 load/counter register high nibble register
PORTA data register
PORTB data register
PORTC data register
PORTD data register
Reserved
Bit1-0: Bonding option
Table Branch register
Pseudo index register
Data pointer for INX low nibble register
Data pointer for INX middle nibble register
Data pointer for INX high nibble register
Bit0: PORTA.1, PORTA.2 as Alarm O/P control register
Bit1: Heavy load Mode control register
Bit2: LCD display OFF control register
Alarm Envelope Control register
Bit1: PORTC as LCD segment output control register
Bit2: PORTD as LCD segment output control register
Bit3: Port pull-up control register
Reserved
Watchdog timer overflow flag register
PORTA input/output control register
PORTB input/output control register
PORTC input/output control register
PORTD input/output control register
Reserved
5
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