NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K)
NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K)
NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K)
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-10600 / PC3(L)-12800 / PC3-14900
Registered DDR3 SDRAM DIMM
Based on DDR3-1333/1600/1866 256Mx8 (2GB/4GB) / 512Mx4 (4GB/8GB) SDRAM G-Die
Features
•Performance:
Speed Sort
DIMM CAS Latency
fck – Clock Frequency
tck – Clock Cycle
fDQ – DQ Burst Frequency
PC3-10600
-CG
9
667
1.5
1333
PC3-12800
-DI
11
800
1.25
1600
PC3-14900
-EK
13
933
1.07
1866
MHz
ns
Mbps
• Programmable Operation:
- DIMM
Latency: 5,6,7,8,9,10,11,12,13
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
• Two different termination values (Rtt_Nom & Rtt_WR)
• 15/10/1 (row/column/rank) Addressing for 2GB
• 15/11/1 (row/column/rank) Addressing for 4GB (512Mx4 Device)
• 15/10/2 (row/column/rank) Addressing for 4GB (256Mx8 Device)
• 15/11/2 (row/column/rank) Addressing for 8GB
• Extended operating temperature rage
• Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
• SDRAMs are in 78-ball BGA Package
• RoHS compliance and Halogen free
Unit
• 240-Pin Registered Dual In-Line Memory Module (RDIMM)
• 2GB/4GB: 256Mx72/512Mx72 DDR3 Registered DIMM based on
256Mx8 DDR3 SDRAM G-Die devices
• 4GB/8GB: 512Mx72/1024Mx72 DDR3 Registered DIMM based
on 512Mx4 DDR3 SDRAM G-Die devices
• Intended for 667MHz/800MHz/933MHz applications
• Inputs and outputs are SSTL-15 compatible
•V
DD
= V
DDQ
= 1.5V ± 0.075V (for DDR3)
•V
DD
= V
DDQ
= 1.35V -0.0675/+0.1V (for DDR3L)
(Backward Compatible to V
DD
= V
DDQ
= 1.5V ±0.075V)
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Nominal and Dynamic On-Die Termination support
Description
NT2GC72B89G0NL(K) / NT2GC72C89G0NL (K)/ NT4GC72B4PG0NL(K) / NT4GC72C4PG0NL(K)/ NT4GC72B8PG0NL(K) /
NT4GC72C8PG0NL(K)/ NT8GC72B4NG0NL(K) and NT8GC72C4NG0NL(K) are 240-Pin Double Data Rate 3 (DDR3) Synchronous
DRAM Registered Dual In-Line Memory Module, organized as one rank of 256Mx72 (2GB), one rank or two ranks of 512Mx72 (4GB) and
two ranks of 1Gx72 (8GB) high-speed memory array. Modules use nine 256Mx8 (2GB) 78-ball BGA packaged devices, eighteen 256Mx8
(4GB) 78-ball BGA packaged devices and thirty-six 512Mx4 (8GB) 78-ball BGA packaged devices. These DIMMs are manufactured using
raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation
between suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving
footprint.
The DIMM is intended for use in applications operating of 667MHz/800MHz/933MHz clock speeds and achieves high-speed data transfer
rates of 1333Mbps/1600Mbps/1866Mbps. Prior to any access operation, the device
latency and burst/length/operation type must be
programmed into the DIMM by address inputs A0-A14 and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.1
10/2011
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K)
NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K)
NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K)
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-10600 / PC3(L)-12800 / PC3-14900
Registered DDR3 SDRAM DIMM
Ordering Information
Part Number
NT2GC72B89G0NL(K)-CG DDR3-1333
NT2GC72B89G0NL(K)-DI
DDR3-1600
NT4GC72B4PG0NL(K)-CG DDR3-1333
NT4GC72B4PG0NL(K)-DI DDR3-1600
NT4GC72B4PG0NL(K)-EK DDR3-1866
NT4GC72B8PG0NL(K)-CG DDR3-1333
NT4GC72B8PG0NL(K)-DI DDR3-1600
NT8GC72B4NG0NL(K)-CG DDR3-1333
NT8GC72B4NG0NL(K)-DI DDR3-1600
NT8GC72B4NG0NL(K)-EK DDR3-1866
NT2GC72C89G0NL(K)-DI
PC3-10600
PC3-12800
PC3-10600
PC3-12800
PC3-14900
PC3-10600
PC3-12800
PC3-10600
PC3-12800
PC3-14900
Speed
667MHz (1.5ns @ CL = 9)
800MHz (1.25ns @ CL = 11)
667MHz (1.5ns @ CL = 9)
800MHz (1.25ns @ CL = 11)
933MHz (1.07ns @ CL = 13)
667MHz (1.5ns @ CL = 9)
800MHz (1.25ns @ CL = 11)
667MHz (1.5ns @ CL = 9)
800MHz (1.25ns @ CL = 11)
933MHz (1.07ns @ CL = 13)
667MHz (1.5ns @ CL = 9)
800MHz (1.25ns @ CL = 11)
667MHz (1.5ns @ CL = 9)
800MHz (1.25ns @ CL = 11)
667MHz (1.5ns @ CL = 9)
800MHz (1.25ns @ CL = 11)
667MHz (1.5ns @ CL = 9)
800MHz (1.25ns @ CL = 11)
1Gx72
512Mx72
1.35V
256Mx72
1Gx72
Gold
512Mx72
1.5V
Organization
256Mx72
Power
Leads
Note
NT2GC72C89G0NL(K)-CG DDR3L-1333 PC3L-10600
DDR3L-1600 PC3L-12800
NT4GC72C4PG0NL(K)-CG DDR3L-1333 PC3L-10600
NT4GC72C4PG0NL(K)-DI DDR3L-1600 PC3L-12800
NT4GC72C8PG0NL(K)-CG DDR3L-1333 PC3L-10600
NT4GC72C8PG0NL(K)-DI DDR3L-1600 PC3L-12800
NT8GC72C4NG0NL(K)-CG DDR3L-1333 PC3L-10600
NT8GC72C4NG0NL(K)-DI DDR3L-1600 PC3L-12800
Note : L is Inphi Register, K is IDT Register.
Pin Description
Pin Name
CK0, CK1
,
CKE0, CKE1
-
A0-A9, A11,
A13-A14
A10/AP
A12/
BA0-BA2
SCL
SDA
Par_In
NC
Description
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Auto-Precharge
Address Input/Burst Chop
SDRAM Bank Address Inputs
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Parity bit for the Address and Control bus
Parity error found on the Address and Control bus
No Connect
Pin Name
ODT0, ODT1
DQ0-DQ63
DQS0-DQS17
-
Description
Active termination control lines
Data input/output
Data strobes
Data strobes complement
TDQS9-TDQS17 Termination data strobes
-
Termination data strobes
DM0-DM8
CB0-CB7
V
REFDQ
, V
REFCA
V
DDSPD
Vtt
V
SS
V
DD
Data Masks
ECC Check Bits
Temperature event pin
Reset pin
Input/Output Reference
SPD and Temp sensor power
Termination voltage
Ground
Core and I/O power
SA0, SA1, SA2 Serial Presence Detect Address Inputs
REV 1.1
10/2011
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K)
NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K)
NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K)
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-10600 / PC3(L)-12800 / PC3-14900
Registered DDR3 SDRAM DIMM
DDR3 SDRAM Pin Assignment
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Front
V
REFDQ
V
SS
DQ0
DQ1
V
SS
Pin
121
122
123
124
125
Back
V
SS
DQ4
DQ5
V
SS
DM0/DQS9/
TDQS9
NC/
/
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
DQ25
V
SS
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8
V
SS
CB2
CB3
V
SS
V
TT
/NC
V
TT
/NC
CKE0
V
DD
BA2
/NC
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
V
SS
DM3/DQS12
/TDQS12
NC/
/
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Front
A2
V
DD
NC
NC
V
DD
V
DD
V
REFCA
Par_In/NC
Pin
181
182
183
184
185
186
187
188
189
Back
A1
V
DD
V
DD
CK0
V
DD
A0
V
DD
BA1
V
DD
V
DD
ODT0
A13
V
DD
/NC
V
SS
DQ36
DQ37
V
SS
DM4/DQS13
/TDQS13
NC/
/
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front
DQ41
V
SS
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SCL
SA2
V
TT
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
V
SS
DM5/DQS14
/TDQS14
NC/
/
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8/DQS17
/TDQS17
NC/
/
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6/DQS15
/TDQS15
NC/
/
126
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/DQS10
/TDQS10
NC/
/
V
DD
A10/AP 190
BA0
V
DD
V
DD
/NC
191
192
193
194
195
196
V
SS
CB6
CB7
V
SS
NC
CKE1/NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7/DQS16
/TDQS16
NC/
/
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/DQS11
/TDQS11
NC/
/
ODT1/NC
197
V
DD
/NC
V
SS
DQ32
DQ33
V
SS
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
198
199
200
201
202
203
204
205
206
207
208
209
210
V
DD
A15
A14
V
DD
A12/
A9
V
DD
A8
A6
V
DD
A3
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA1
SDA
V
SS
V
TT
V
DD
A11
A7
V
DD
A5
A4
V
DD
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
Note: 1. CKE1,
and ODT1 are for 2GB/4GB/8GB only.
2.
and
are for 8GB only.
3. TDQS9-TDQS17 and
-
are for 1GB/2GB only.
REV 1.1
10/2011
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K)
NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K)
NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K)
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-10600 / PC3(L)-12800 / PC3-14900
Registered DDR3 SDRAM DIMM
Input/Output Functional Description
Symbol
CK0, CK1
,
CKE0, CKE1
Type
Polarity
Cross
point
Active
High
Function
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of
.
A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock. However,
CK1 and
are terminated but not used on RDIMMs.
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enable the command decoders for the associated rank of SDRAM when low and disables
decoders when high. When decoders are disabled, new commands are ignored and previous
operations continue. Other combinations of these input signals perform unique functions,
including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing
internal control words in the register device(s). For modules with two registers,
and
operate
similarly to
and
for the second set of register outputs or register control words.
When sampled at the positive rising edge of CK and falling edge of
,
signals
,
,
define the operation to be executed by the SDRAM.
Asserts on-die termination for DQ, DM, DQS, and
signals if enabled via the DDR3 SDRAM
mode register.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.
signals are complements, and timing is relative to the cross point of respective DQS and
.
If the module is to be operated in single ended strobe mode, all
signals must be tied on
the system board to V
SS
and DDR3 SDRAM mode registers programmed appropriately.
TDQS/ is applicable for x8 DRAMs only. When enabled via mode register A11=1 in MR1,
DRAM will enable the same termination resistance function on TDQS/ that is applied to
DQS/. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data
mask function
is not used. X4/x16 DRAMs must disable the TDQS function via mode
register A11=0 in MR1.
-
Selects which DDR3 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of
.
During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
.
In addition to the column address, AP is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
Data Input/Output pins.
Check bits are used for ECC.
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
Reference voltage for SSTL15 inputs.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
A resistor must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a pull
up.
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
Address pins used to select the Serial Presence Detect and Temp sensor base address.
The
pin is reserved for use to flag critical module temperature.
This signal resets the DDR3 SDRAM.
Parity bit for the Address and Control bus.
Parity error detected on the Address and Control bus. A resistor may be connected from bus line
to
V
DD
on the system planar to act as a pull up.
Input
Input
–
Input
Active
Low
,
,
ODT0, ODT1
DM0 – DM8
Input
Input
Input
Active
Low
Active
High
Active
High
DQS0 – DQS17
–
I/O
Cross
point
TDQS9 – TDQS17
–
BA0, BA1, BA2
Output
Input
A0 – A9
A10/AP
A11
A12/
A13-A14
Input
-
DQ0 – DQ63
CB0 – CB7
V
DD
,
V
DDSPD,
V
SS
V
REFDQ,
V
REFCA
SDA
SCL
SA0 – SA2
Par_In
Input
-
-
-
-
-
-
-
-
-
-
-
I/O
Supply
Supply
I/O
Input
Input
Output
Input
Input
Output
REV 1.1
10/2011
4
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K)
NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K)
NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K)
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-10600 / PC3(L)-12800 / PC3-14900
Registered DDR3 SDRAM DIMM
Functional Block Diagram (Part 1 of 2)
[2GB
–
1 Rank, 256Mx8 DDR3 SDRAMs]
PCK0A
P
RCKE0A
RODT0A
A[14:0]A/
BA[2:0]A
PCK0A
P
RCKE0B
RODT0B
A[14:0]B/
BA[2:0]B
DQS4
DM4/DQS13
DQ[39:32]
DQS
TDQS
DQ[7:0]
ZQ
D4
DQS5
DM5/DQS14
DQ[47:40]
DQS
TDQS
DQ[7:0]
DQS6
DM6/DQS15
DQ[55:48]
DQS
TDQS
DQ[7:0]
DQS7
DM7/DQS16
DQ[63:56]
DQS
TDQS
DQ[7:0]
V
tt
V
DDSPD
V
DD
V
TT
V
REFCA
V
REFDQ
V
SS
SPD w/ Integrated Thermal Sensor
SCL
SA0
SA1
SA2
SCL
A0
A1
A2
DQS8
DM8/DQS17
CB[7:0]
DQS
TDQS
DQ[7:0]
ZQ
D8
CK
CKE
ODT
A[14:0]
BA[2:0]
DQS3
DM3/DQS12
DQ[31:24]
DQS
TDQS
DQ[7:0]
ZQ
D3
CK
CKE
ODT
A[14:0]
BA[2:0]
DQS2
DM2/DQS11
DQ[23:16]
DQS
TDQS
DQ[7:0]
ZQ
D2
CK
CKE
ODT
A[14:0]
BA[2:0]
DQS1
DM1/DQS10
DQ[15:8]
DQS
TDQS
DQ[7:0]
ZQ
D1
DQS0
DM0/DQS9
DQ[7:0]
DQS
TDQS
DQ[7:0]
ZQ
D0
V
tt
CK
CKE
ODT
A[14:0]
BA[2:0]
CK
CKE
ODT
A[14:0]
BA[2:0]
SPD
D0-D8
D0-D8
D0-D8
D0-D8
D0-D8
CK
CKE
ODT
A[14:0]
BA[2:0]
CK
CKE
ODT
A[14:0]
BA[2:0]
ZQ
D7
CK
CKE
ODT
A[14:0]
BA[2:0]
ZQ
D6
CK
CKE
ODT
A[14:0]
BA[2:0]
ZQ
D5
SDA
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. ZQ resistors are 240Ω
±1%.
For all other resistor values refer to the appropriate wiring diagram.
REV 1.1
10/2011
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
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