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AT17LV256-10TQC

器件型号:AT17LV256-10TQC
器件类别:存储   
文件大小:214KB,共24页
厂商名称:Atmel (Microchip)
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器件描述

2M X 1 CONFIGURATION MEMORY, PQCC20

参数
参数名称属性值
功能数量1
端子数量20
最大工作温度85 Cel
最小工作温度-40 Cel
最大供电/工作电压3.6 V
最小供电/工作电压3 V
额定供电电压3.3 V
最大时钟频率10 MHz
加工封装描述塑料, MS-018AA, LCC-20
状态DISCONTINUED
工艺CMOS
包装形状SQUARE
包装尺寸芯片 CARRIER
表面贴装Yes
端子形式J BEND
端子间距1.27 mm
端子涂层锡 铅
端子位置
包装材料塑料/环氧树脂
温度等级INDUSTRIAL
内存宽度1
组织2M × 1
存储密度2.10E6 deg
操作模式同步
位数2.10E6 words
位数2M
内存IC类型配置存储器
串行并行串行

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Features
EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,
2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
Supports both 3.3V and 5.0V Operating Voltage Applications
In-System Programmable (ISP) via Two-Wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX
®
, APEX
Devices, Lucent ORCA
®
, Xilinx XC3000
, XC4000
, XC5200
, Spartan
®
, Virtex
®
FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and
44-lead TQFP Packages
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
High-reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for
Commercial Parts (at 70°C)
FPGA
Configuration
EEPROM
Memory
AT17LV65
AT17LV128
AT17LV256
AT17LV512
AT17LV010
AT17LV002
AT17LV040
3.3V and 5V
System Support
Description
The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-
to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-
lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1. The
AT17LV series Configurators uses a simple serial-access procedure to configure one
or more FPGA devices. The user can select the polarity of the reset function by pro-
gramming four EEPROM bytes. These devices also support a write-protection
mechanism within its programming mode.
The AT17LV series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1.
AT17LV Series Packages
AT17LV65/
AT17LV128/
AT17LV256
Yes
Yes
Yes
Yes
Yes
(2)
AT17LV512/
AT17LV010
Yes
Yes
Use 8-lead LAP
(1)
Yes
Yes
(2)
Package
8-lead LAP
8-lead PDIP
8-lead SOIC
20-lead PLCC
20-lead SOIC
44-lead PLCC
44-lead TQFP
Notes:
AT17LV002
Yes
Use 8-lead LAP
(1)
Yes
Yes
(2)
Yes
Yes
AT17LV040
(3)
(3)
Yes
Yes
1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-
lead SOIC package is not available for the AT17LV512/010/002 devices, it is possi-
ble to use an 8-lead LAP package instead.
2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the
AT17LV512/010/002 devices.
3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.
Rev. 2321E–CNFG–06/03
1
Pin Configuration
8-lead LAP
DATA
CLK
(WP
(1)
) RESET/OE
CE
1
2
3
4
8
7
6
5
VCC
SER_EN
CEO (A2)
GND
8-lead SOIC
DATA
CLK
(1)
(WP ) RESET/OE
CE
1
2
3
4
8
7
6
5
VCC
SER_EN
CEO (A2)
GND
8-lead PDIP
DATA
CLK
(1)
(WP ) RESET/OE
CE
1
2
3
4
8
7
6
5
VCC
SER_EN
CEO (A2)
GND
20-lead PLCC
NC
DATA
NC
VCC
NC
3
2
1
20
19
NC
GND
NC
NC
NC
9
10
11
12
13
CLK
(WP1 ) NC
(1)
(WP ) RESET/OE
(WP2
(2)
) NC
CE
(2)
4
5
6
7
8
18
17
16
15
14
NC
SER_EN
NC
NC (READY
(2)
)
CEO (A2)
Notes:
1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
2
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
20-lead SOIC
(1)
NC
DATA
NC
CLK
NC
RESET/OE
NC
CE
NC
GND
Note:
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
NC
NC
SER_EN
NC
NC
CEO (A2)
NC
NC
NC
1. This pinout only applies to AT17LV65/128/256 devices.
20-lead SOIC
(1)
DATA
NC
CLK
NC
NC
NC
NC
RESET/OE
NC
CE
Note:
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
NC
SER_EN
NC
NC
NC
NC
CEO
NC
GND
1. This pinout only applies to AT17LV512/010/002 devices.
3
2321E–CNFG–06/03
44 PLCC
NC
CLK
NC
NC
DATA
NC
VCC
NC
NC
SER_EN
NC
44
43
42
41
40
39
38
37
36
35
34
NC
CLK
NC
NC
DATA
NC
VCC
NC
NC
SER_EN
NC
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO/A2
NC
18
19
20
21
22
23
24
25
26
27
28
(WP1
(1)
)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
44 TQFP
NC
NC
NC
NC
NC
NC
(1)
(WP1 )
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
Note:
1. This pin is only available on AT17LV002 devices.
4
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO(A2)
NC
AT17LV65/128/256/512/010/002/040
Block Diagram
SER_EN
WP1
(2)
WP2
(2)
POWER ON
RESET
READY
(2)
(1)
Notes:
1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17LV series configurator. If CE is held High after
the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-
stated. When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
5
2321E–CNFG–06/03
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