EN29PL064/032
EN29PL064/032
64/32 Mbit (4/2 M x 16-Bit) CMOS 3.0 Volt- only,
Simultaneous-Read/Write Flash Memory
Distinctive Characteristics
Architectural Advantages
•
64/32 Mbit Page Mode devices
- Page size of 4 words: Fast page read access
from random locations within the page
•
Single power supply operation
- Voltage range of 2.7V to 3.3V valid for MCP
product
- Single Voltage, 2.7V to 3.6V for Read and Write
operations
•
Simultaneous Read/Write Operation
- Data can be continuously read from one bank
while executing erase/ program functions in
another bank
- Zero latency switching from write to read
operations
•
FlexBank Architecture( PL064/PL032)
- 4 separate banks, with up to two simultaneous
operations per device
- Bank A:
PL064 - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032 - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
- Bank B:
PL064 - 24 Mbit (32 Kw x 48)
PL032 - 12 Mbit (32 Kw x 24)
- Bank C:
PL064 - 24 Mbit (32 Kw x 48)
PL032 - 12 Mbit (32 Kw x 24)
- Bank D:
PL064 - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032 - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
•
Secured Silicon Sector region
- Up to 64 customer-lockable words
•
Both top and bottom boot blocks in one device
•
Data Retention: 20 years typical
•
Cycling Endurance: 100K cycles per sector
typical
Performance Characteristics
•
-
-
-
•
-
-
-
High Performance
Page access times as fast as 25 ns
Random access times as fast as 70 ns
32-word/64-byte write buffer reduces overall
programming time for multiple-word updates
Power consumption (typical values at 10 MHz)
45 mA active read current
17 mA program/erase current
0.2 µA typical standby mode current
Software Features
•
Software command-set compatible with
JEDEC 42.4 standard
•
CFI (Common Flash Interface) compliant
- Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
•
Erase Suspend / Erase Resume
- Suspends an erase operation to allow read or
program operations in other sectors of same
bank
•
Program Suspend / Program Resume
- Suspends a program operation to allow read
operation from sectors other than the one
being programmed
•
Unlock Bypass Program command
- Reduces overall programming time when
issuing multiple program command
sequences
Hardware Features
•
Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting
program or erase cycle completion
•
Hardware reset pin (RESET#)
- Hardware method to reset the device to reading
array data
•
WP#/ ACC (Write Protect/Acceleration) input
- At V
IL
, hardware level protection for the first and
last two 4K word sectors.
- At V
IH
, allows removal of sector protection
- At V
HH
, provides accelerated programming in a
factory setting
•
Persistent Sector Protection
- A command sector protection method to lock
combinations of individual sectors and sector
groups to prevent program or erase operations
within that sector
- Sectors can be locked and unlocked in-system at
V
CC
level
•
Package options
- 56-ball Fine Pitch BGA
- 48-ball Fine pitch BGA
- 48-pin TSOP-1
This Data Sheet may be revised by subsequent versions
1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2008/03/27
EN29PL064/032
GENERAL DESCRIPTION
The PL064/PL032 is a 64/32 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash
memory device organized as 4/2 Mwords. The devices are offered in the following packages:
– 7 mm x 9 mm, 56-Ball Fine-pitch BGA standalone (PL064/PL032)
– 8 mm x 6 mm, 48-ball Fine-pitch BGA standalone (PL032)
– 48-pin TSOP (PL064/PL032)
The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in
standard EPROM programmers. A 11.0 volt V
PP
is not required for write or erase operations.
The device offers fast page access times of 25 ns, with corresponding random access times of 70
ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate
bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2008/03/27
EN29PL064/032
1. Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the
memory space into 4 banks, which can be considered to be four separate memory arrays as far as
certain operations are concerned. The device can improve overall system performance by allowing a
host system to program or erase in one bank, then immediately and simultaneously read from
another bank with zero latency (with two simultaneous operations operating at any one time). This
releases the system from waiting for the completion of a program or erase operation, greatly
improving system performance.
The device can be organized in both top and bottom sector configurations. The banks are organized
as follows:
Bank
A
B
C
D
PL064 Sectors
8 Mbit (4 Kw x 8 and 32 Kw x 15)
24 Mbit (32 Kw x 48)
24 Mbit (32 Kw x 48)
8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032 Sectors
4 Mbit (4 Kw x 8 and 32 Kw x 7)
12 Mbit (32 Kw x 24)
12 Mbit (32 Kw x 24)
4 Mbit (4 Kw x 8 and 32 Kw x 7)
1.1 Page Mode Features
The page size is 4 words. After initial page access is accomplished, the page mode operation
provides fast read access speed of random locations within that page.
1.2 Standard Flash Memory Features
The device requires a
single 3.0 volt power supply
(2.7 V to 3.6 V) for both read and write
functions. Internally generated and regulated voltages are provided for the program and erase
operations.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash
standard.
Commands are written to the command register using standard microprocessor write
timing. Register contents serve as inputs to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch addresses and data needed for the
programming and erase operations. Reading data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program command sequence. The Unlock Bypass
mode facilitates faster programming times by requiring only two write cycles to program data instead
of four. Device erasure occurs by executing the erase command sequence.
The host system can detect whether a program or erase operation is complete by reading the DQ7
(Data# Polling) and DQ6 (toggle)
status bits.
After a program or erase cycle has been completed,
the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write
operations during power transitions. The hardware sector protection feature disables both program
and erase operations in any combination of sectors of memory. This can be achieved in-system or
via programming equipment.
The Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any period of
time to read data from, or program data to, any sector that is not selected for erasure. True
background erase can thus be achieved. If a read is needed from the Secured Silicon Sector area
(One Time Program area) after an erase suspend, then the user must use the proper command
sequence to enter and exit this region.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2008/03/27
EN29PL064/032
The
Program Suspend/Program Resume
feature enables the user to hold the program operation
to read data from any sector that is not selected for programming. If a read is needed from the
Secured Silicon Sector area, Persistent Protection area, or the CFI area, after a program suspend,
then the user must use the proper command sequence to enter and exit this region.
The device offers two power-saving features. When addresses have been stable for a specified
amount of time, the device enters the
automatic sleep mode.
The system can also place the device
into the standby mode. Power consumption is greatly reduced in both these modes.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2008/03/27
EN29PL064/032
2. Ordering Information
EN29PL064
-
70
T
I
P
PACKAGING CONTENT
(Blank) = Conventional
P = Pb Free
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
T = 48-pin TSOP
B = 48-Ball Fine Pitch Ball Grid Array (FBGA)
0.80mm pitch, 6mm x 8mm package
C =56-Ball Fine Pitch Ball Grid Array (FBGA)
0.80mm pitch, 7mm x 9mm package
SPEED
70 = 70ns
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
29PL = FLASH, 3.0V Read Program Erase,
Simultaneous-Read/Write, Page-Mode
064 = 64 Megabit (4 M x 16-Bit)
032 = 32 Megabit (2 M x 16-Bit)
3. Product Selector Guide
Part Number
Speed Option
V
CC
= 2.7 V – 3.6 V
EN29PL032 / EN29PL064
70
70
25
Max Access Time, ns (t
ACC
)
Max CE# Access , ns (t
CE
)
Max Page Access, ns (t
PACC
)
Max OE# Access, ns (t
OE
)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2008/03/27
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