- 1 -11
TM58PC10
1. Feature
ROM: 1K x 14 bits
RAM: 25 x 8 bits
STACK: 2 Levels
I/O ports: 12 I/O PAD
Timer/counter: 8bits x1 (TMR0)
Prescaler: 8 Bits
Watchdog Timer: On chip WDT is based on internal RC oscillator. The shortest period is
20mS; user can extend the WDT overflow period to 2.6S by using
prescaler.
Power-On Reset
Reset Timer: 20 mS (5V)
Four external Oscillate modes: RC, LP Crystal, NT Crystal and HS Crystal.
Operation Voltage: 2.2V∼5.5V
Instruction set: 79
Reset vector: 3FFH
1
tenx technology, inc.
Rev 1.0 2004/3/5
- 2 -22
TM58PC10
2. Pin Definition & Pad Assignment
PA
2
PA
3
RTCC
RESETB/VPP
VSS
PB
0
PB
1
PB
2
PB
3
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PA
1
PA
0
OSC
1
OSC
2
VDD
PB
7
PB
6
PB
5
PB
4
Package Types : DIP & SOP.
PA
2
PA
3
RTCC
RESETB/VPP
VSS
VSS
PB0
PB1
PB2
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
PA
1
PA
0
OSC1
OSC2
VDD
VDD
PB7
PB6
PB5
PB4
PB3 10
Package Type : SSOP.
RTCC
RESETB/VPP
VSS
PB
0
PB
1
PB
2
PB
3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OSC
1
OSC
2
VDD
PB
7
PB
6
PB
5
PB
4
Package Types : DIP & SOP.
2
tenx technology, inc.
Rev 1.0 2004/3/5
- 3 -33
TM58PC10
PIN description
Pin name
RTCC
PA
3-0
PB
7-0
RESETB/VPP
OSC
1
OSC
2
VDD
VSS
I/O
I
I/O
I/O
I
I
O
Description
External clock input to TMR0 counter
I/O port
I/O port
System reset signal & VPP (High voltage) input
1 Low voltage: reset mode
2 High voltage: programming mode
Oscillator input
Oscillator output
P Power input
P Ground input
I: Input; O: Output; I/O: Bi-direction; P: Power
3. Control Register
Name
CONFIG
(Instruction)
SELECT
IAR
TMR0
PC
STATUS
BSR
I/O Port
A
I/O Port
B
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CPT
SUR
0
EDGE
0
PSA
$00
$01
$02
$03
$04
$05
$06
PB
7
PB
6
PB
5
PB
4
D
7
D
7
D
6
D
6
D
5
D
5
SA
0
A
4
D
4
D
4
TOB
D
4
A
3
D
3
D
3
PDB
D
3
PA
3
PB
3
Bit 2
Bit 1
Bit 0
WDTE FOSC
1
FOSC
0
PS
2
A
2
D
2
D
2
Z
D
2
PA
2
PB
2
PS
1
A
1
D
1
D
1
DC
D
1
PA
1
PB
1
PS
0
A
0
D
0
D
0
C
D
0
PA
0
PB
0
3
tenx technology, inc.
Rev 1.0 2004/3/5
- 4 -44
TM58PC10
4. System Block Diagram
Instruction
Register
PB
7
~
0
I/O Port
PA
3
~
0
Instruction
Decoder
Program
Counter
EPROM
2 Level
stacks
Data Bus
TMR
0
Select
Register
Status
Acc
BSR
WDT/TMR
0
Prescaler
ALU and Control
Unit
25 bytes RAM
Watch Dog
Timer
Sleep
RTCC
Oscillator
C
onfiguration
Word
i
OSC
1
OSC
2
RESETB/VPP
4
tenx technology, inc.
Rev 1.0 2004/3/5
- 5 -55
TM58PC10
5. Memory Map
TM58PC10 memory is organized into program memory and data memory.
5.1 Program memory
TM58PC10 allow directly goto any address in 1K memories without limited by page size.
In addition, lcall and lgoto instructions are employed to provide flexible addressing mode.
TM58PC10 has a 10-bits program counter capable of accessing 1K spaces. If accessing
address has over 1K, then the address will map to physical 1K memories, i.e. 1K+M will be
mapped to M. A NOP at the reset vector location will cause a restart at address 000h. A
simple map to induce illustrate ROM organization is shown in figures 5-1.
000H
…
…
Program
...
…
3FEH
3FFH
Reset vector
Figure 5-1 The ROM Organization
5
tenx technology, inc.
Rev 1.0 2004/3/5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
