PMC
FEATURES
Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
• Memory Organization
- Pm25LV512: 64K x 8 (512 Kbit)
- Pm25LV010: 128K x 8 (1 Mbit)
Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
- Uniform 32 Kbyte blocks (8 sectors per block)
- Two blocks with 32 Kbytes each (512 Kbit)
-
Four blocks with 32 Kbytes each (1 Mbit)
- 128 pages per block
Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
High Performance Read
- 25 MHz clock rate (maximum)
Page Mode for Program Operations
- 256 bytes per page
Pm25LV512 / Pm25LV010
512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory
With 25 MHz SPI Bus Interface
Block Write Protection
-
The Block Protect (BP1, BP0) bits allow part or entire
of the memory to be configured as read-only.
Hardware Data Protection
- Write Protect (WP#) pin will inhibit write operations
to the status register
•
Page Program (up to 256 Bytes)
- Typical 2 ms per page program time
•
Sector, Block and Chip Erase
- Typical 40 ms sector/block/chip erase time
Single Cycle Reprogramming for Status Register
-
Build-in erase before programming
High Product Endurance
- Guarantee 100,000 program/erase cycles per single
sector (preliminary)
- Minimum 20 years data retention
Industrial Standard Pin-out and Package
- 8-pin JEDEC SOIC
- 8-contact WSON
- Optional lead-free (Pb-free) packages
GENERAL DESCRIPTION
The Pm25LV512/010 are 512 Kbit/1 Mbits 3.0 Volt-only serial Flash memories. These devices are designed to use
a single low voltage, range from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations.
The devices can be programmed in standard EPROM programmers as well.
The device is optimized for use in many commercial applications where low-power and low-voltage operation are
essential. The Pm25LV512/010 is enabled through the Chip Enable pin (CE#) and accessed via a 3-wire interface
consisting of Serial Data Input (Sl), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are com-
pletely self-timed.
Block Write protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled
by programming the status register. Separate write enable and write disable instructions are provided for additional
data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts
to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial
sequence.
The Pm25LV512/010 are manufactured on PMC’s advanced nonvolatile CMOS technology, P-FLASH™. The de-
vices are offered in 8-pin JEDEC SOIC and 8-contact WSON packages with operation frequency up to 25 MHz.
Programmable Microelectronics Corp.
1
Issue Date: February, 2004, Rev: 1.4
PMC
CONNECTION DIAGRAMS
Pm25LV512/010
CE#
SO
WP#
GND
1
2
3
4
8
7
6
5
Vcc
HOLD#
SCK
SI
CE#
SO
WP#
GND
1
2
3
4
8
Vcc
HOLD#
SCK
SI
Top View
7
6
5
8-Pin SOIC
8-Contact WSON
PIN DESCRIPTIONS
SYMB OL
TYPE
D ESC R IPTION
C hi p Enable: C E# goes low acti vates the devi ce's i nternal ci rcui tri es for
devi ce operati on. C E# goes hi gh deselects the devi ce and swi tches i nto
standby mode to reduce the power consumpti on. When the devi ce i s not
selected, data wi ll not be accepted vi a the seri al i nput pi n (Sl), and the
seri al output pi n (SO) wi ll remai n i n a hi gh i mpedance state.
Seri al D ata C lock
Seri al D ata Input
Seri al D ata Output
Ground
D evi ce Power Supply
INPUT
INPUT
Wri te Protect: When the WP# pi n brought to low and WPEN bi t i s "1", all
wri te operati ons to the status regi ster are i nhi bi ted.
Hold: Pause seri al communi cati on wi th the master devi ce wi thout
resetti ng the seri al sequence.
C E#
INPUT
SC K
SI
SO
GND
V cc
WP#
HOLD #
INPUT
INPUT
OUTPUT
Programmable Microelectronics Corp.
2
Issue Date: February, 2004, Rev: 1.4
PMC
SERIAL INTERFACE DESCRIPTION
Pm25LV512/010
Pm25LV512/010 can be driven by a microcontroller on the SPI bus as shown in Figure 1. The serial communication
term definitions are in the following section.
MASTER:
The device that generates the serial clock.
SLAVE:
Because the Serial Clock pin (SCK) is always an input, the Pm25LV512/010 always operates as a slave.
TRANSMITTER/RECEIVER:
The Pm25LV512/010 has separate pins designated for data transmission (SO) and
reception (Sl).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE:
After the device is selected with CE# going low, the first byte will be received. This byte
contains the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no data will be shifted into the Pm25LV512/010, and the serial
output pin (SO) will remain in a high impedance state until the falling edge of CE# is detected again. This will
reinitialize the serial communication.
Figure 1. Bus Master and SPI Memory Devices
SDO
SPI Interface with
(0, 0) or (1, 1)
SDI
SCK
SCK
Bus Master
SPI Memory
Device
CS3
CS2 CS1
CE#
WP# HOLD# CE#
WP# HOLD# CE#
WP# HOLD#
SPI Memory
Device
SPI Memory
Device
SO
SI
SCK SO
SI
SCK
SO
SI
Note: 1. The Write Protect (WP#) and Hold (HOLD#) si gnals should be driven, High or Low as appropriate.
Programmable Microelectronics Corp.
5
Issue Date: February, 2004, Rev: 1.4
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