Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040
512 Kbit / 1Mbit / 2Mbit / 4Mbit 3.0 Volt-only CMOS Flash Memory
FEATURES
Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
• Memory Organization
- Pm39LV512: 64K x 8 (512 Kbit)
- Pm39LV010: 128K x 8 (1 Mbit)
- Pm39LV020: 256K x 8 (2 Mbit)
- Pm39LV040: 512K x 8 (4 Mbit)
• High Performance Read
- 55/70 ns access time
• Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
- Uniform 64 Kbyte blocks (sector group - except
Pm39LV512)
• Data# Polling and Toggle Bit Features
• Hardware Data Protection
• Automatic Erase and Byte Program
- Build-in automatic program verification
-
Typical 16 µs/byte programming time
- Typical 55 ms sector/block/chip erase time
• Low Power Consumption
- Typical 4 mA active read current
- Typical 8 mA program/erase current
- Typical 0.1 µA CMOS standby current
• High Product Endurance
- Guarantee 100,000 program/erase cycles per
single sector (preliminary)
- Minimum 20 years data retention
• Industrial Standard Pin-out and Packaging
- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional lead-free (Pb-free) package
GENERAL DESCRIPTION
The Pm39LV512/010/020/040 are 512 Kbit/1 Mbit/2 Mbit/4 Mbit 3.0 Volt-only Flash Memories. These devices are
designed to use a single low voltage, range from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and
program operations. The 12.0 Volt V
PP
power supply for program and erase operations are not required. The devices
can be programmed in standard EPROM programmers as well.
The memory array of Pm39LV512 is divided into uniform 4 Kbyte sectors for data or code storage. The memory
arrays of Pm39LV010/020/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks (sector group -
consists of sixteen adjacent sectors). The sector or block erase feature allows users to flexibly erase a memory
area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in others.
The chip erase feature allows the whole memory array to be erased in one single erase operation. The devices can
be programmed on a byte-by-byte basis after performing the erase operation.
The devices have a standard microprocessor interface as well as a JEDEC standard pin-out/command set. The
program operation is executed by issuing the program command code into command register. The internal control
logic automatically handles the programming voltage ramp-up and timing. The erase operation is executed by
issuing the chip erase, block, or sector erase command code into command register. The internal control logic
automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been
programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit functions, the
progress or completion of program and erase operations can be detected by reading the Data# Polling on I/O7 or
the Toggle Bit on I/O6.
The Pm39LV512/010/020/040 are manufactured on pFLASH™’s advanced nonvolatile CMOS technology. The de-
vices are offered in 32-pin VSOP and PLCC packages with 70 ns access time.
Chingis Technology Corporation
1
Issue Date: April, 2006 Rev:1.6
Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040
CONNECTION DIAGRAMS
39LV040
WE#
WE#
WE# WE#
A12
A15
A16
A18
39LV020
V
CC
A12
A15
A16
39LV512 39LV010
A12
A15
A16
NC
V
CC
V
CC
NC
A12
A15
NC
NC
V
CC
39LV040 39LV020 39LV010 39LV512
NC
NC
A17
A17
39LV512 39LV010 39LV020 39LV040
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
14
39LV512
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE#
A10
CE#
I/O7
A14
A13
A8
A9
A11
OE#
A10
CE#
I/O7
A14
A13
A8
A9
A11
OE#
A10
CE#
I/O7
A14
A13
A8
A9
A11
OE#
A10
CE#
I/O7
15
I/O2
16
GND
17
I/O3
18
I/O4
19
I/O5
I/O5
I/O5
I/O5
20
I/O6
I/O6
I/O6
I/O6
39LV010
I/O1
I/O1
I/O3
I/O3
I/O3
39LV020
GND
I/O1
GND
I/O2
39LV040
I/O1
I/O2
32-Pin PLCC
39LV040
39LV020
39LV010
39LV512
GND
I/O2
I/O4
I/O4
I/O4
39LV512
39LV010
39LV020
39LV040
A11
A9
A8
A13
A14
A17
WE#
V
CC
A18
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
32-Pin VSOP
Chingis Technology Corporation
2
Issue Date: April, 2006 Rev: 1.6
Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040
PRODUCT ORDERING INFORMATION
Pm39LVxxx
-70
J
C
E
Environmental Attribute
E = Lead-free (Pb-free) Package
Blank = Standard Package
Temperature Range
C = Commercial (0°C to +85°C)
Package Type
J = 32-pin Plastic J-Leaded Chip Carrier (32J)
V = 32-pin Thin Small Outline Package
(VSOP - 8 mm x 14 mm)(32V)
Speed Option
-
70 = 70ns
Device Number
Pm39LV512 (512 Kbit)
Pm39LV010 (1 Mbit)
Pm39LV020 (2 Mbit)
Pm39LV040 (4 Mbit)
Part Number
Pm39LV512-70JCE
32J
Pm39LV512-70JC
70
Pm39LV512-70VCE
32V
Pm39LV512-70VC
Pm39LV010-70JCE
32J
Pm39LV010-70JC
70
Pm39LV010-70VCE
32V
Pm39LV010-70VC
Pm39LV020-70JCE
32J
Pm39LV020-70JC
70
Pm39LV020-70VCE
32V
Pm39LV020-70VC
Pm39LV040-70JCE
32J
Pm39LV040-70JC
70
Pm39LV040-70VCE
32V
Pm39LV040-70VC
Chingis Technology Corporation
Issue Date: April, 2006 Rev: 1.6
t
ACC
(ns)
Package
Temperature Range
Commercial
(0
o
C to +85
o
C)
3
Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040
PIN DESCRIPTIONS
SYMBOL
A0 - A
MS(1)
TYPE
INPUT
DESCRIPTION
Address Inputs: For memory addresses input. Addresses are internally
latched on the falling edge of WE# during a write cycle.
Chip Enable: CE# goes low activates the device's internal circuitries for
device operation. CE# goes high deselects the device and switches into
standby mode to reduce the power consumption.
Write Enable: Activate the device for write operation. WE# is active low.
Output Enable: Control the device's output buffers during a read cycle. OE#
is active low.
Data Inputs/Outputs: Input command/data during a write cycle or output data
during a read cycle. The I/O pins float to tri-state when OE# are disabled.
Device Power Supply
Ground
No Connection
CE#
INPUT
WE#
OE#
I/O0 - I/O7
V
CC
GND
NC
INPUT
INPUT
INPUT/
OUTPUT
Note:
1. A
MS
is the most significant address where A
MS
= A15 for Pm39LV512, A16 for Pm39LV010, A17 for
Pm39LV020, and A18 for Pm39LV040.
Chingis Technology Corporation
4
Issue Date: April, 2006 Rev: 1.6
Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040
BLOCK DIAGRAM
ERASE/PROGRAM
VOLTAGE
GENERATOR
I/O0-I/O7
I/O BUFFERS
HIGH VOLTAGE
SWITCH
WE#
CE#
OE#
COMMAND
REGISTER
CE,OE LOGIC
DATA
LATCH
SENSE
AMP
ADDRESS
LATCH
Y-DECODER
X-DECODER
Y-GATING
MEMORY
ARRAY
A0-A
M S
DEVICE OPERATION
READ OPERATION
The access of Pm39LV512/010/020/040 are similar to
EPROM. To read data, three control functions must be
satisfied:
• CE# is the chip enable and should be pulled low
( V
IL
).
• OE# is the output enable and should be pulled
low ( V
IL
).
• WE# is the write enable and should remains high
( V
IH
)
.
PRODUCT IDENTIFICATION
The product identification mode can be used to identify
the manufacturer and the device through hardware or
software read ID operation. See Table 1 for pFLASH™
Manufacturer ID and Device ID. The hardware ID mode is
activated by applying a 12.0 Volt on A9 pin, typically
used by an external programmer for selecting the right
programming algorithm for the devices. Refer to Table 2
for Bus Operation Modes. The software ID mode is acti-
vated by a three-bus-cycle command. See Table 3 for
Software Command Definition.
Chingis Technology Corporation
BYTE PROGRAMMING
The programming is a four-bus-cycle operation and the
data is programmed into the devices (to a logical “0”) on
a byte-by-byte basis. See Table 3 for Software Com-
mand Definition. A program operation is activated by writ-
ing the three-byte command sequence followed by pro-
gram address and one byte of program data into the
devices. The addresses are latched on the falling edge
of WE# or CE# whichever occurs later, and the data are
latched on the rising edge of WE# or CE# whichever
occurs first. The internal control logic automatically
handles the internal programming voltages and timing.
A data “0” can not be programmed back to a “1”. Only
erase operation can convert the “0”s to “1”s. The Data#
Polling on I/O7 or Toggle Bit on I/O6 can be used to
detect the progress or completion of a program cycle.
5
Issue Date: April, 2006 Rev: 1.6
FPGA/CPLD
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