BL7448SM Intelligent 8K-bit
EEPROM
Description
BL7448SM is an IC Card chip (module) made
by 0.35um CMOS EERPOM process. It has
1024 byte EEPROM with logical encryption
and function.
Figure 1
Features
•
•
•
•
•
•
•
•
•
1024 x 8 bit EEPROM organization
Byte-wise addressing
Irreversible byte-wise write protection of every Byte
1024 x1 bit organization of protection memory
Serial three-wire link
End of processing indicated at data output
Minimum of 100,000 write/erase cycles
Data retention time :>10 years
Contacts configuration and serial interface according to ISO 7816 standard
(synchronous transmission)
Data can only be changed after entry of the correct 2-byte
Programmable security code
Pin Description
Pin No.
1
2
3
4
5
6
7
8
Parameter
C1
C2
C3
C4
C5
C6
C7
C8
Symbol
V
dd
RST
CLK
N.C.
GND
NC
I/O
NC
Function Description
Supply Voltage
Reset signal
Clock input
Not connected
Ground
Not connected
Bidirectional data line (open drain)
Not connected
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BL7448SM Intelligent 8K-bit
EEPROM
Function Description
Block Diagram
Figure 2
The BL7448SM consists of 1024
x
8 bit EEPROM main memory and a 1024-bit protection-memory
With PROM functionality .The main memory can be irreversibly protected against data change by writing the
corresponding bit in the protection memory. Once written the protection bit cannot be erased. The main
memory is erased and written byte by byte. Normally a data change consists of an erase and write
procedure. It depends on the contents of the data byte in the main memory and the new data byte whether
the EEPROM is really erased and/or written. If none of the 8 bits in the addressed byte requires a zero-to-
one transition the erase access will be suppressed. Vice versa the write access will be suppressed if no one-
to-zero transition is necessary.
Additionally to the above functions the BL7448SM provides a security code logic, which
controls the write/erase access to the memory. For this purpose, the BL7448SM contains a 3-
byte security memory with an error counter EC and 2 bytes reference data. These 2 bytes as a
whole are called programmable security code (PSC). After power on the whole memory, except
for the reference data, the memory can only be read. (The value of PSC is “00”)Writing and
erasing is only possible after a successful comparison of verification data with the internal
reference data.
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BL7448SM Intelligent 8K-bit
EEPROM
After eight successive unsuccessful comparisons the error counter blocks any subsequent
attempt, and hence any possibility to write and erase.
Reset and Answer-to-Reset
*Reset
After connecting the operating voltage to Vcc, the chip will hold and wait the operation of reset. The
operation of reset begins with RST from L to H, and ends with CLK from L to H. During the operation of
reset, all commands will be ignored.
After power on reset, the operation of reading must be execute before data can be altered.
.
*Answer-to-Reset
Answer-to-Reset set the address counter to zero and output the first data. The other data can be read
with CLK signal.
Command
RST
RST
1
0
I/O
Command Input
Data Output
Command
Byte1
S0
S1
S2
S3
S4
S5
A8
A9
Byte2
Address
A0~A7
Byte3
Data
D0~D7
Operation
Updata main
memory
& protection memory
Updata main
memory
Write protection
memory
Read main memory
& protection memory
Read main memory
Mode
1
0
0
0
1
1
Data
Processing
1
0
0
0
1
0
0
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
V
CC
RST
CLK
I/O
1
2
1
3
2
3
Data
Comp. data
No effect
No effect
Processing
Processing
Data Output
Data Output
31
32
31
32
IC sets I/O
to State H
RST
t
d4
t
d4
t
d2
t
H
t
L
CLK
I/O
t
d5
Figure 3 Reset and Answer-to-Reset
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BL7448SM Intelligent 8K-bit
EEPROM
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
S0 S1 S2 S3 S4 S5 A8 A9 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7
Bute 1
Control Byte
Bute 2
Address
Bute 3
Data
Figure 4 Command Input
Command Mode
Write/Erase Operation
Write/Erase,
except for
protection-memory
Note: Write means from H to L, Erase means from L to H
There are three kinds of Write/Erase operations:
Erase and Write (The number of clock pulses=203, frequency <=20KHZ)
Write only: means the 8 bits in the addressed byte from H to L( The number of clock pulses =103,
frequency <=20KHZ)
Erase only(=FF; The number of clock pulses =103, frequency <= 20KHZ)
Write/Erase, include protection-memory
As shipped, the protection-memory has been erased, it can be written only once.
Write protection-memory and compare data
When comparison of the entered data byte is same as the assigned byte in the EEPROM. the
protection-memory is written.
After sent a certain CLK, the command of Write/Erase will be over. After operation, the state of I/O pin
will be changed from H to L.
The I/O state can be changed when RST change from L to H.
Command Input
RES
CLK
E/W
Internal signal
0
23
0
1
2
TE
99
102
TW
199
202
Processing
I/O
S0 S1
D6 D7
Figure 5 Erase and Write timing
Command Input
RES
CLK
E/W
Internal signal
0
23
0
1
2
TE
99
102
TW
199
202
Processing
I/O
S0 S1
D6 D7
Figure 6 Only Write or Erase
Read operation
Read main memory (See Figure 7)
This operation don’t read the protection-memory. After 8 CLK, the address of memory will be increased
by additional pulse .
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BL7448SM Intelligent 8K-bit
EEPROM
Read main memory and protection-memory (See Figure 8)
After input this command, the next 8 CLK will read out 8 bits data; the ninth CLK will read out the
content of protection-memory. After 9 CLK, the address of memory will be increased by additional
pulse.
Security code verification
Byte1
0
1
1
1
0
0
0
1
1
0
1
1
1
0
0
1
0
0
1
1
1
1
1
1
Byte2
Address
253
254
255
Byte3
Address
Bit mask
PSC byte1
PSC byte2
Operation
Write error
counter
Verification 1
st
PSC byte
nd
Verification 2
PSC byte
Mode
Processing
Processing
Processing
Cmad
omn
Ipt
nu
RT
S
CK
L
IO
/
Satn Ades
trig drs
A A
8 9
D D
6 7
rno
adm
vle
au
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
Dt Otu
aa upt
Satn Ades
trig drs
Satn Ades+1
trig drs
Satn Ades+n
trig drs
Figure 7 Read main memory
Dt
aa
CmadIpt
omn nu
RT
S
Otu
upt
CK
L
0
2
3
IO
/
A A
8 9
D D
6 7
rno
adm
vle
au
0 1 2 3 4 5 6 7 P 0 1 2 3 4 5 6 7 P
0
0
P 0 1 2 3 4 5 6 7 P
0
0
Satn Ades
trig drs
Satn Ades
trig drs
Satn Ades+
trig drs 1
Satn Ades+n
trig drs
Figure 8
read main
memory and protection-memory
Security code verification
User verification operation
BL7448SM only can read when the security code verification is unsuccessful. The content of security code
cannot be read out. If you try to read security code, you only can get “00”
The processing is:
*Write a bit of EC(the bit is not written before), the address of EC is “1021”
*Input the first byte of PSC, the address is “1022”
*Input the second byte of PSC, the address is “1023”
*If the security verification is successful , the EC can be erased.
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