BL7432SM Low voltage Intelligent 2K bits
EEPROM
Description
BL7432SM is an IC for Chip Card made by
0.35um CMOS EERPOM process. It has 256
bytes EEPROM with write protect function .
It
can be operated at low voltage. With its contact
configuration in accordance to ISO standard
7816.BL7432SM can be widely used in different
types of IC memory cards.
Figure 1
Features
•
•
•
•
•
•
•
•
•
•
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256 x 8 bit EEPROM organization
Byte-wise addressing
Irreversible byte-wise write protection of lowest 32 addresses (Byte 0 ……31)
32 x1 bit organization of protection memory
Two-wire link protocol
End of processing indicated at data output
Answer-to-Reset according to ISO standard 7816-3
Programming time 2.5 ms per byte for both erasing and writing
Minimum of 100,000 write/erase cycles
Data retention time :>10 years
Contacts configuration and serial interface according to ISO 7816 standard (synchronous
transmission)
Pin Description
Pin No.
1
2
3
4
5
6
7
8
Parameter
C1
C2
C3
C4
C5
C6
C7
C8
Symbol
V
dd
RST
CLK
N.C.
GND
NC
I/O
NC
Function Description
Supply Voltage
Reset signal
Clock input
Not connected
Ground
Not connected
Bidirectional data line (open drain)
Not connected
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BL7432SM Low voltage Intelligent 2K bits
EEPROM
Function Description
Block Diagram
M a in
m e m o ry
P ro te c tio n
m e m o ry
255
EEPROM
256X8
32
31
0
A d d res s
31
Area for
perma nent
da ta stora ge
0
A d d ress
D a ta
D a ta
8
M e m o ry
M ain /P rotection
S ecu rity
5
H V G e n e ra to r
C u rre n t
G e n e ra to r
D e co d e r
C olu m n
S a m p lin g
A d d . D a ta
R e g is te r
,
C o m p a ra to r
P ro g ra m
C o n tro l
R eset
B lock Logi
c
L o g ic
S e q ue nc e r
A nd
S e c urity
In terfac e
VCC
GND
I/O R S T C L K
Figure 2
The BL7432SM consists of 256 x 8 bit EEPROM main memory (figure 2) and a 32-bit
protection-memory with PROM functionality .The main memory is erased and written byte by
byte. When erased, all 8 bits of a data byte are set to logical one. When written, the information in
the individual EEPROM cells is to the input data, altered bit by bit to logical zeros (logical AND
between the old and the new data in the EEPROM).
Normally a data change consists of an erase and write procedure. It depends on the
contents of the data byte in the main memory and the new data byte whether the EEPROM is
really erased and/or written. If none of the 8 bits in the addressed byte requires a zero-to-one
transition the erase access will be suppressed. Vice versa the write access will be suppressed if
no one-to-zero transition is necessary. The write and the erase operation takes at least 2.5 ms
each. The first 32 bytes can be irreversibly protected against data change by writing the
corresponding bit in the protection memory. Each data byte in this address range is assigned to
one bit of the protection memory and has the same address as the data byte in the main memory
which it is assigned to. Once written the protection bit cannot be erased.
Transmission Protocol
The transmission protocol is a two wire link protocol between the interface device IFD and
the integrated circuit IC. It is identical to the protocol type “S=10”. All data changes on I/O are
initiated by the falling edge on CLK.
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BL7432SM Low voltage Intelligent 2K bits
EEPROM
The transmission protocol consists of the 4 modes:
1) Reset and Answer-to-Reset
2) Command Mode
3) Outgoing Data Mode
4) Processing Mode
(1) Reset and Answer-to-Reset
Answer-to-Reset takes place according to ISO standard 7816-3. The reset can be given at
any time during operation. In the beginning, the address counter id set to zero together with a
clock pulse and the first data bit (LSB) is output to I/O when RST is set from state H to state L.
Under a continuous input of additional 31 clock pulses the contents of the first 4 EEPROM
rd
addresses can be read out. The 33 clock pulse switches I/O to state H (figure 3). During
Answer-to-Reset any start and stop condition is ignored.
VCC
RST
1
CLK
1
I/O
2
3
...
30
31
32
2
3
4
...
31
32
RST
td4
td4
tH
tL
CLK
td2
I/O
td5
Figure 3 Reset and Answer-to-Reset
(2) Command Mode
After the Answer-to-Reset the chip waits for a command. Every command begins with a start condition,
includes a 3 bytes long command entry followed by an additional clock pulse and ends with a stop condition
(figure 4).
--Start condition: Falling edge on I/O during CLK in state H
--Stop condition: Rising edge on I/O during CLK in state H
Command
1
CLK
2
3
4
23
24
IFD sets I/O to State L
I/O
START
From IFD
CLK
td1
tBUF
I/O
tF
td7
STOP
From IFD
tR
td5
td8
td3
tL
Figure 4 Command Mode
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BL7432SM Low voltage Intelligent 2K bits
EEPROM
After the reception of a command there are two possible modes:
--Outgoing data mode for reading
--Processing mode for writing and erasing
(3) Outgoing Data Mode
In this mode the IC sends data to the IFD. Figure 5 shows the timing diagram. The first bit becomes
valid on I/O after the first falling edge on CLK. After the last data bit an additional clock pulse is necessary in
order to set I/O to state H and to prepare the IC for a new command entry. During this mode any start and
stop condition is discarded.
Command
CLK
1
2
3
4
n-1
n
IC sets I/O to State H
I/O
1
Start of Outgoing Data
2
3
n-1
n
Figure 5 Outgoing Data Mode
(4) Processing Mode
In this mode the IC processes internally. Figure 6 shows the timing diagram. The IC has to be clocked
continuously until I/O which was switched to state L after the first falling edge of CLK is set to state H. Any
start and stop condition id discarded during this mode.
CLK
I/O
1
2
3
n-1
n
Start of
Processing
td2
td2
End of
Processing
Figure 6 Processing Mode
Commands
(1) Command Format
Each command consists of three byte:
MSB Control
LSB
MSB Address
LSB
MSB Data
LSB
B7 B6 B5 B4 B3 B2 B1 B0
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
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BL7432SM Low voltage Intelligent 2K bits
EEPROM
Beginning with the control byte LSB is transmitted first.
Byte 1 Control
B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
Byte 2
Address
A7~A0
Address
Address
No effect
Address
Byte 3
Data
D7~D0
No effect
Input data
No effect
Input data
Operation
Mode
Read Main
Memory
Update
Main Memory
Read Protection
Memory
Write Procection
Memory
Outgoing data
Processing
Outgoing Data
Processing
(2) Description of Command
Read Main Memory
The command reads out the contents of the main memory(with LSB first)starting at the given byte
address(N) UP TO THE END MEMORY. After the command entry the IFD has to supply sufficient
clock pulses. The number of clocks is m=(256-N)*8+1.The read access to the main memory is
always possible.
Read Protection Memory
The command transfers the protection bits under a continuous input of 32 clock pulses to the
output. I/O is switched to state H by an additional pulse. The protection memory can always be
read.
Update Main Memory
The command programs the address EEPROM byte with the data byte transmitted. Depending
on the old and new data, one of the following sequences will take place during the processing
mode:
-- erase and write
(5.0ms) corresponding to m = 255 clock pulses
-- write without erase
(2.5ms) corresponding to m = 124 clock pulses
-- erase without write
(2.5ms) corresponding to m = 124 clock pulses
(all values at 50 kHZ clock rate)
Command Entry
CLK
I/O
RST
1
2
1
3
2
24
Processing
1
24
2
3
m-2 m-1
m
Figure 7 Update Main Memory
Write Protection Memory
The execution of this command contains a comparison of the entered data byte with the assigned
byte in the EEPROM .In case of identity the protection bit is written thus making the data
information unchangeable. If the data comparison results in data differences writing of the
protection bit will be suppressed. Execution times and required clock pulses see Update Main
Memory.
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